Semiconductor devices having self-aligned bodies and methods of forming the same

Abstract

A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

1 . A semiconductor device comprising: 
 a source region and a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region;    a gate pattern on the channel region and the body region; and    a contact connecting the gate pattern to the body region,    wherein a sidewall of the body region extension is aligned with a sidewall of the gate pattern.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the source region, drain region, channel region and body region extension are on an insulation layer.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the body contact extends through the gate pattern to the body region extension.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the body contact is on a surface of the gate pattern and is in contact with a sidewall of the body region extension.  
   
   
       5 . The semiconductor device of  claim 1 , wherein at least one of the source region or the drain region includes a portion elevated to have a height greater than a height of the channel region and/or the body region extension.  
   
   
       6 . The semiconductor device of  claim 5 , further comprising a sidewall spacer on a sidewall of the gate pattern, 
 wherein the source region and the drain region are adjacent to the sidewall spacer.    
   
   
       7 . The semiconductor device of  claim 1 , wherein the channel region and the body region extension have the same conductivity type and the body region extension is more heavily doped than the channel region.  
   
   
       8 . A semiconductor device comprising: 
 a semiconductor substrate;    an active region defined in the semiconductor substrate;    a lower gate pattern crossing over the active region;    an interlayer dielectric covering the active region and the lower gate pattern;    a body region on the interlayer dielectric;    an upper gate pattern on the body region; and    a contact electrically connecting the upper gate pattern and the body region to the lower gate pattern,    wherein the body region includes a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from one end of the channel region, the body region extension being in electrical contact with the body contact; and    a sidewall of the body region extension is aligned to a sidewall of the upper gate pattern.    
   
   
       9 . The semiconductor device of  claim 8 , wherein the body region at least partially overlaps the lower gate pattern.  
   
   
       10 . The semiconductor device of  claim 8 , further comprising a contact pattern electrically connecting one of the source region or the drain region to the active region.  
   
   
       11 . The semiconductor device of  claim 8 , wherein the contact extends through the upper gate pattern and the interlayer dielectric to connect to the lower gate pattern.  
   
   
       12 . The semiconductor device of  claim 8 , wherein the contact is on a surface of the gate pattern and extends through the interlayer dielectric to connect to a sidewall of the body region extension and the lower gate pattern.  
   
   
       13 . The semiconductor device of  claim 8 , wherein at least one of the source region or the drain region includes a portion elevated to have a height greater than the height of the channel region and/or the body region extension.  
   
   
       14 . The semiconductor device of  claim 13 , further comprising: 
 a capping layer on the upper gate pattern; and    a sidewall spacer on a sidewall of the upper gate pattern,    wherein the sidewall of the body region extension is aligned to the sidewall spacer; and    the elevated portion of the source and drain regions is adjacent to the sidewall spacer.    
   
   
       15 . The semiconductor device of  claim 14 , wherein the elevated portion of the source and/or drain region comprises a conductive pattern that is adjacent to the sidewall spacer and that has a sidewall aligned to the sidewall of the body region extension.  
   
   
       16 . The semiconductor device of  claim 8 , wherein the body region extension and the channel region have the same conductivity type and the body region extension is doped more heavily than the channel region.  
   
   
       17 . A method of forming a semiconductor device, comprising: 
 forming a gate pattern on a semiconductor layer;    forming a mask pattern on portions of the semiconductor layer disposed on opposite sides of and adjacent to the gate pattern;    etching the semiconductor layer using the mask pattern and the gate pattern as an etch mask to form a body region having a sidewall aligned with a sidewall of the gate pattern, the body region including a body region extension extending beneath the gate pattern and away from a portion of the body region defined by the mask pattern;    selectively doping portions of the body region disposed on opposite sides of and adjacent to the gate pattern to form a source region and a drain region and to define a channel region between the source region and the drain region; and    forming a contact to electrically connect the gate pattern to the body region extension.    
   
   
       18 . The method of  claim 17 , further comprising selectively doping the body region extension.  
   
   
       19 . The method of  claim 17 , wherein forming the mask pattern comprises: 
 forming a sidewall spacer on a sidewall of the gate pattern;    forming a capping layer on the gate pattern;    forming a semiconductor mask layer to cover the gate pattern and exposed portions of the semiconductor layer around the gate pattern;    thinning the semiconductor mask layer to expose the capping layer; and    patterning the semiconductor mask layer to form a mask pattern covering portions of the semiconductor layer disposed on opposite sides of and adjacent to the gate pattern.    
   
   
       20 . The method of  claim 19 , wherein thinning the semiconductor mask layer comprises chemical-mechanical polishing the semiconductor mask layer.  
   
   
       21 . The method of  claim 19 , further comprising: 
 implanting impurities into the semiconductor mask pattern and the body region extension; and    removing a top of the mask pattern to form a semiconductor pattern on the body region.    
   
   
       22 . A method of forming a semiconductor device, comprising: 
 defining an active region in a semiconductor layer;    forming a lower gate pattern, the lower gate pattern crossing over the active region;    forming an interlayer dielectric over the lower gate pattern and the active region;    forming a semiconductor layer on the interlayer dielectric;    forming an upper gate pattern on the semiconductor layer;    forming a mask pattern to cover portions of the semiconductor layer disposed on opposite sides of and adjacent to the upper gate pattern;    using the mask pattern and the upper gate pattern as an etch mask, etching the semiconductor layer to form a body region including a portion extending to opposite sides of the gate pattern and a body region extension having a sidewall extending along the upper gate pattern, the sidewall of the body region aligned to a sidewall of the end of the upper gate pattern;    selectively doping portions of the body region disposed on opposite sides of and adjacent to the upper gate pattern to form a source region and a drain region and to define a channel region between the source region and the drain region; and    forming a contact to electrically connect the upper gate pattern and the body region extension to the lower gate pattern.    
   
   
       23 . The method of  claim 22 , further comprising selectively doping the body region extension.  
   
   
       24 . The method of  claim 22 , wherein 
 forming the mask pattern comprises: 
 forming a sidewall spacer on a sidewall of the gate pattern;  
 forming a capping layer on the gate pattern;  
 forming semiconductor mask layer to cover the gate pattern and exposed portions of the semiconductor layer around the gate pattern;  
 thinning the semiconductor mask layer to expose the capping layer; and  
 patterning the semiconductor mask layer to form a mask pattern covering portions of the semiconductor layer disposed on opposite sides of and adjacent to the gate pattern.  
   
   
   
       25 . The method of  claim 24 , wherein thinning the semiconductor mask layer comprises chemical-mechanical polishing the semiconductor mask layer.  
   
   
       26 . The method of  claim 22 , further comprising: 
 implanting impurities into the semiconductor mask pattern and the body region extension; and    removing a top of the mask pattern to form a semiconductor pattern on the body region.    
   
   
       27 . The method of  claim 22 , wherein forming the contact comprises: 
 forming an upper dielectric on a surface of the substrate where the source and drain regions are formed;    forming a contact hole through the upper dielectric, the upper gate pattern, the body region, and the lower interlayer dielectric to expose the lower gate pattern; and    filling the contact hole with a conductive layer.    
   
   
       28 . The method of  claim 22 , wherein the forming the contact comprises: 
 forming an upper dielectric on a surface of the substrate where the source region and the drain region are formed;    forming a contact hole through the upper dielectric and the lower interlayer dielectric to expose the upper gate pattern, a sidewall of the body region, and the lower gate pattern; and    filling the contact hole with a conductive layer electrically connecting the upper gate pattern and the sidewall of the body region to the lower gate pattern.