Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern

Abstract

Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

1 - 21 . (canceled)  
   
   
       22 . A field effect transistor comprising; 
 a semiconductor substrate;    a gate stack on a top surface of the semiconductor substrate;    a first spacer formed on the sidewall of the gate stack;    a silicide, in or on the semiconductor substrate, having an edge adjacent to the first spacer;    a second spacer covering the surface of the first spacer and at least the edge of the silicide adjacent to the first spacer.    
   
   
       23 . The field effect transistor according to  claim 22 , wherein the second spacer covers the surface of the first spacer and at least the edge of the silicide adjacent to the first spacer so that the semiconductor substrate is not exposed between the second spacer and the silicide.