Mold assembly, method and a package stack via bottom-leaded plastic (BLP) packaging

Abstract

A packaged semiconductor device and method has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

1 . An assembly for a semiconductor die and a lead frame package comprising: 
 a top mold plate having a top and a plurality of sides of a mold assembly in a transfer molding operation; and    a generally planar bottom mold plate of a mold assembly having portions thereof engaging portions of said top mold plate during said transfer molding operation, said top mold plate and said bottom mold plate forming a mold cavity having a top, having a bottom, having sidewalls and having end walls when engaged, said top mold plate and said bottom mold plate for suspending a semiconductor die and a portion of said lead frame within said mold cavity for injecting a material to encapsulate said semiconductor die and portions of said leadframe therein, one sidewall of said sidewalls having an inner surface with grooves and columns for forming columns and grooves in at least one external surface of said molded package.    
     
     
         2 . The assembly of  claim 1 , wherein the grooves in the inner surface of the one of the sidewalls have side portion surfaces angled to provide an opening dimension greater than an inner dimension of the grooves, the angle being in the range of  5  to  15  degrees.  
     
     
         3 . A semiconductor device assembly, comprising: 
 a semiconductor die;    a leadframe including at least one lead with upper, lower and edge surfaces, said lead comprising: 
 an inner end conductively connected to said die;  
 an intermediate portion configured for connection to a first electrical apparatus; and  
 an outer lead configured for connection to second electrical apparatus; and  
   a package enclosure enclosing said die and the inner end of said at least one lead, said enclosure having top, bottom and side surfaces, said bottom surface of said intermediate portion of said at least one lead is generally coplanar with said bottom surface of said package enclosure and exposed for electrical connection to a lead of another electrical apparatus.    
     
     
         4 . The semiconductor device of  claim 3 , wherein portions of the package enclosure adjacent the edges of said intermediate portion of said lead are excised to expose at least a portion of said lead edges.  
     
     
         5 . The semiconductor device of  claim 4 , wherein said excised portion comprises an elongate chamfer exposing a portion of the lead edge comprising between about  0 . 1  and about  1 . 0  of the lead thickness.  
     
     
         6 . The semiconductor device of  claim 5 , wherein the angle formed by the chamfer with the lead edge is between about 20 and about 60 degrees.  
     
     
         7 . The semiconductor device of  claim 4 , wherein the excised portions have a generally uniform depth from the surface of said package enclosure.  
     
     
         8 . The semiconductor device of  claim 3 , wherein the generally coplanar bottom lead surface is excised to submerge said lead surface into said bottom surface of said package enclosure a distance of up to about one-half the lead thickness.  
     
     
         9 . The semiconductor device of  claim 8 , further comprising an excised portion of said package enclosure immediately adjacent said bottom lead.  
     
     
         10 . The semiconductor device of  claim 9 , wherein said excised portion of said package comprises a chamfer.  
     
     
         11 . The semiconductor device of  claim 3 , wherein said another electrical apparatus comprises one of a semiconductor device, electrical conduit, and circuit board.  
     
     
         12 . The semiconductor device of  claim 3 , wherein said package enclosing said die and said at least one lead comprises a polymer.  
     
     
         13 . The semiconductor device of  claim 3 , wherein said outer leads are bent upwardly to form an inverted J configuration.  
     
     
         14 . The semiconductor device of  claim 3 , wherein said at least one outer lead is configured to be a truncated coplanar outward extension of said intermediate lead portion.  
     
     
         15 . The semiconductor device of  claim 14 , wherein said at least one outer lead extends a distance of about 8 to 30 mils from said package surface.  
     
     
         16 . The semiconductor device of  claim 14 , wherein said at least one outer lead extends a distance of about  10  to  20  mils from said package surface.  
     
     
         17 . The semiconductor device of  claim 14 , wherein said outer lead has top and bottom surfaces, whereby both surfaces are configured for electrical connection to other electrical apparatus.  
     
     
         18 . The semiconductor device of  claim 14 , wherein portions of the package enclosure adjacent the edges of said intermediate portion of said at least one lead are excised to expose at least a portion of said lead edges.  
     
     
         19 . The semiconductor device of  claim 14 , wherein the generally coplanar bottom lead surface is excised to submerge said lead surface into said bottom surface of said package enclosure.  
     
     
         20 . The semiconductor device of  claim 3 , wherein said at least one lead is lanced adjacent a side surface of said package enclosure, whereby said lead has no outer lead portion.  
     
     
         21 . The semiconductor device of  claim 20 , wherein the lanced lead portion coplanar with said side surface comprises an electrical connection surface.  
     
     
         22 . The semiconductor device of  claim 1 , wherein a side surface of said package enclosure includes a vertical groove for enclosing said outer lead in a vertical orientation.  
     
     
         23 . A method for forming a semiconductor device, comprising: 
 providing a semiconductor die;    forming a lead frame having at least one lead;    preparing a semiconductor die-leadframe assembly including electrical connections between the semiconductor die and at least one lead of the leadframe;    aligning the die-leadframe assembly in the cavity of a mold assembly having a top plate and a bottom plate wherein an intermediate portion of at least one lead is adjacent to the floor of said bottom plate;    closing the mold assembly and injecting fluid polymeric encapsulant to fill the mold cavity; removing the molded polymeric package from said mold assembly; and    configuring said outer leads to a desired configuration.    
     
     
         24 . The method of  claim 23 , comprising the further step of: curing the encapsulant.  
     
     
         25 . The method of  claim 23 , comprising the further step of: 
 deflashing the bottom of the package and portions of outer leads to remove flash residue from attachment areas of said leads.    
     
     
         26 . The method of  claim 23 , comprising the further step of: 
 lancing the leadframe to singulate the outer leads.    
     
     
         27 . The method of  claim 23 , comprising the further step of plating said attachment areas of said leads with tin.  
     
     
         28 . The method of  claim 23 , comprising the further step of excising portions of said polymeric package adjacent and parallel to said intermediate portion of the at least one lead.  
     
     
         29 . The method of  claim 23 , wherein said excised portions of said package are excised by an erosion method.