Latch-up prevention for memory cells

Abstract

A method of fabricating a memory cell and corresponding memory cell structure are provided. According to the method, a pull-up transistor and a pull-down transistor are formed in a semiconductor structure of the memory cell. The pull-up transistor is coupled to the pull down transistor. The pull-up transistor is coupled to a contact within said semiconductor structure such that the pull-up transistor is coupled to a voltage input through parasitic resistance of the semiconductor structure. Additional embodiments are disclosed.

1 . A method of fabricating a memory cell comprising a pull-up transistor and a pull-down transistor formed in a semiconductor structure of said memory cell, said method comprising: 
 coupling said pull-up transistor to said pull down transistor; and    coupling said pull-up transistor to a contact within said semiconductor structure such that said pull-up transistor is coupled to a voltage input through parasitic resistance of said semiconductor structure.    
   
   
       2 . A method of fabricating a memory cell as claimed in  claim 1 , wherein said method further comprising: 
 providing a substrate assembly having at least one semiconductor layer; and    forming said semiconductor structure within said at least one semiconductor layer.    
   
   
       3 . A method of fabricating a memory cell as claimed in  claim 2  wherein said method further comprises: 
 forming an access transistor in said at least one substrate assembly, said access transistor having one terminal coupled to said pull-up transistor and said pull down transistor.    
   
   
       4 . A method of fabricating a memory cell as claimed in  claim 3  wherein said access transistor further comprises an additional terminal and an access gate, said additional terminal coupled to a column line of a memory array and said access gate coupled to a row line of said memory array.  
   
   
       5 . A method of fabricating a memory cell as claimed in  claim 2  said method further comprising: 
 forming a source, a drain, and a gate of a said pull-up transistor in said semiconductor structure;    forming a source, a drain, and a gate of a said pull-down transistor in said semiconductor structure;    coupling said drain of a said pull-up transistor to said drain of a said pull-down transistor; and    coupling said gate of a said pull-up transistor to said gate of a said pull-down transistor.    
   
   
       6 . A method of fabricating a memory cell as claimed in  claim 5  said method further comprising: 
 forming a first contact and a second contact within said semiconductor structure;    coupling said source of a said pull-up transistor to one of said first and second contacts; and    coupling the other of said first and second contacts to a first voltage input such that said source of said pull-up transistor is coupled to said first voltage input through a parasitic resistance defined by said semiconductor structure.    
   
   
       7 . A method of fabricating a memory cell as claimed in  claim 1  said method further comprising: 
 forming a source, a drain, and a gate of a said pull-up transistor in said semiconductor structure;    forming a source, a drain, and a gate of a said pull-down transistor in said semiconductor structure;    forming a first contact and a second contact within said first semiconductor structure such that said first contact is formed a first distance from said source of said pull-up transistor and said second contact is formed a second distance from said source of said pull-up transistor, wherein said first distance defines a first component of said parasitic resistance and said second distance defines a second component of said parasitic resistance.    
   
   
       8 . A method of fabricating a memory cell as claimed in  claim 7  said method further comprising: 
 forming a first parasitic bi-polar transistor including a base, wherein said base is coupled to said first contact through said second component of said parasitic resistance and to said second contact through said first component of said parasitic resistance.    
   
   
       9 . A method of fabricating a memory cell as claimed in  claim 7  wherein said first and second contacts are formed such that said first component of said parasitic resistance and said second component of said parasitic resistance are connected in series.  
   
   
       10 . A method of fabricating a memory cell as claimed in  claim 7  wherein said first and second contacts are formed such that said first component of said parasitic resistance is at least as large as said second component of said parasitic resistance.  
   
   
       11 . A method of fabricating a memory cell as claimed in  claim 7  wherein said first and second contacts are formed such that said first component of said parasitic resistance is larger than said second component of said parasitic resistance.  
   
   
       12 . A method of fabricating a memory cell as claimed in  claim 7  wherein said source of said pull-up transistor is coupled to one of said first and second contacts by forming an electrically conducting interconnect layer over said semiconductor structure.  
   
   
       13 . A method of fabricating a memory cell as claimed in  claim 7  wherein said pull-up transistor is formed between said first and second contacts.  
   
   
       14 . A method of fabricating a memory cell as claimed in  claim 1  wherein said first pull-up transistor and said first pull-down transistor are configured to form an inverter.  
   
   
       15 . A method of fabricating a memory cell as claimed in  claim 1  wherein said first pull-up transistor and said first pull-down transistor are configured to form a CMOS inverter.  
   
   
       16 . A method of fabricating a memory cell as claimed in  claim 1  wherein said memory cell is configured to define an SRAM memory cell.  
   
   
       17 . A method of fabricating a memory cell comprising a first pull-up transistor and a first pull-down transistor formed in a first semiconductor structure of said memory cell and a second pull-up transistor and a second pull-down transistor formed in a second semiconductor structure of said memory cell, said method comprising: 
 coupling said first pull-up transistor to said first pull down transistor;    coupling said second pull-up transistor to said second pull down transistor;    coupling said first pull-up transistor to a contact within said semiconductor structure such that said first pull-up transistor is coupled to a voltage input through parasitic resistance of said semiconductor structure; and    coupling said second pull-up transistor to a contact within said semiconductor structure such that said second pull-up transistor is coupled to a voltage input through parasitic resistance of said semiconductor structure.    
   
   
       18 . A method of fabricating a memory cell as claimed in  claim 17  wherein said first semiconductor structure and said second semiconductor structure form portions of a single substrate.  
   
   
       19 . A memory cell comprising a pull-up transistor and a pull-down transistor formed in a semiconductor structure of said memory cell, wherein: 
 said pull-up transistor is coupled to said pull down transistor; and    said pull-up transistor is coupled to a contact within said semiconductor structure such that said pull-up transistor is coupled to a voltage input through parasitic resistance of said semiconductor structure.    
   
   
       20 . A memory cell as claimed in  claim 19 , wherein: 
 a source, a drain, and a gate of a said pull-up transistor are formed in said semiconductor structure;    a source, a drain, and a gate of a said pull-down transistor are formed in said semiconductor structure;    a first contact and a second contact are formed within said first semiconductor structure such that said first contact is formed a first distance from said source of said pull-up transistor and said second contact is formed a second distance from said source of said pull-up transistor; and    said first distance defines a first component of said parasitic resistance and said second distance defines a second component of said parasitic resistance.