Non-volatile memory, non-volatile memory cell and operation thereof

Abstract

A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

1 . A non-volatile memory cell, comprising: 
 a substrate;    a charge-trapping layer disposed over the substrate;    a control gate disposed over the charge-trapping layer;    a first dielectric layer disposed between substrate and the charge-trapping layer;    a second dielectric layer disposed between the control gate and the charge-trapping layer;    a first conductive state of a source and a first conductive state of a drain disposed in the substrate on each side of the charge-trapping layer;    a first conductive state of a lightly doped region disposed in the substrate between the source and the charge-trapping layer; and    a second conductive state of a pocket-doped region disposed in the substrate between the drain and the charge-trapping layer.    
   
   
       2 . The non-volatile memory cell of  claim 1 , wherein the charge-trapping layer comprises a silicon nitride layer.  
   
   
       3 . The non-volatile memory cell of  claim 1 , wherein the first conductive state is N-type.  
   
   
       4 . The non-volatile memory cell of  claim 1 , wherein the second conductive state is P-type.  
   
   
       5 . The non-volatile memory cell of  claim 1 , wherein the memory cell also comprises a channel region within the substrate between the source and the drain.  
   
   
       6 . A non-volatile memory, comprising: 
 a substrate;    a plurality of first conductive state of a buried bit lines disposed in the substrate;    a plurality of word lines over the substrate and crossing over the buried bit lines;    a charge-trapping layer disposed between the word lines and the substrate that between the buried bit lines;    a first dielectric layer between the charge-trapping layer and the substrate;    a second dielectric layer between the word lines and the charge-trapping layer;    a first conductive state of a lightly doped region disposed close to the top of the substrate on one side of the buried bit lines; and    a second conductive state of a pocket-doped region disposed in the substrate on another side of the buried bit line.    
   
   
       7 . The non-volatile memory of  claim 6 , wherein the charge-trapping layers comprise silicon nitride layers.  
   
   
       8 . The non-volatile memory of  claim 6 , wherein the first conductive state is N-type.  
   
   
       9 . The non-volatile memory of  claim 6 , wherein the second conductive state is P-type.  
   
   
       10 . The non-volatile memory of  claim 6 , wherein the memory further comprises a channel region disposed in the substrate between the buried bit lines.  
   
   
       11 . The non-volatile memory of  claim 6 , wherein the memory further comprises two bit line selection transistors electrically connected to the buried bit lines.  
   
   
       12 . The non-volatile memory of  claim 6 , wherein the first dielectric layer, the charge-trapping layer and the second dielectric layer are extended over the entire substrate.  
   
   
       13 . A method of operating a non-volatile memory cell having a first conductive state of a first drain, a second drain and a source in a substrate, a word line crossing over the first, the second drain and the source, a charge-trapping layer between the word lines and the substrate that between the first, the second drains and the source, a first dielectric layer between the charge-trapping layer and the substrate, a second dielectric layer between the word lines and the charge-trapping layer, a first conductive state of a lightly doped region close to the top surface of the substrate on one side of each first, the second drain and the source, and a second conductive state of a pocket-doped region on another side of each first, the second drain and the source, the operating method comprising the steps of: 
 performing a programming operation by applying a first bias voltage to the word lines, applying a second bias voltage to the source, connecting the first drain to a ground and setting the second drain to a floating state, wherein the first bias voltage is lower than the second bias voltage.    
   
   
       14 . The operating method of  claim 13 , wherein the method further comprises: 
 performing an erasing operation by applying a bias voltage to the word lines for executing a F-N channeling erase operation, connecting the first drain and the source to a ground and setting the second drain to a floating state.    
   
   
       15 . The operating method of  claim 13 , wherein the method further comprises: 
 performing a reading operation by applying a third bias voltage to the word lines, applying a voltage lower than the third bias voltage to the first drain, connecting the source to a ground and setting the second drain to a floating state.