Semiconductor device manufacturing method, wiring and semiconductor device

Abstract

In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a suicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

1 . A method of manufacturing a semiconductor device including forming a silicide film on a surface of a semiconductor layer, the method comprising: 
 forming in the semiconductor layer a p-type impurity layer, an n-type impurity layer and a (p+n)-type impurity layer between the n-type and p-type impurity layers by introducing impurities;    forming an impurity segregation layer on the n-type and p-type impurity layers and the (p+n)-type impurity layer by heat-treating the semiconductor layer;    removing the impurity segregation layer; and    thereafter forming the silicide film by forming a film of a metallic material on the semiconductor layer and by heat-treating the film of the metallic material.    
   
   
       2 . The method according to  claim 1 , wherein the n-type and p-type impurity layers and the (p+n)-type impurity layer are formed by covering the surface of the semiconductor layer on one side with a first mask, introducing one of the p-type and n-type impurities into a first exposed portion, covering the surface of the semiconductor layer on the other side with a second mask, and introducing the other impurity into a second exposed portion including a doubly exposed portion which is also included in the first exposed portion.  
   
   
       3 . The method according to  claim 1 , wherein polycrystalline Si or polycrystalline SiGe is used as the semiconductor layer.  
   
   
       4 . The method according to  claim 1 , wherein a layer of a compound of the p-type impurity and the n-type impurity is caused to segregate as the impurity segregation layer on the (p+n)-type impurity layer.  
   
   
       5 . The method according to  claim 4 , wherein one of As—B, P—B and As—B—P is caused to segregate as the compound layer.  
   
   
       6 . The method according to  claim 1 , wherein Ni or a compound of Ni and at least one of Pd. Pt and Co is used as the metallic material.  
   
   
       7 . The method according to  claim 1 , wherein the semiconductor layer is formed as a gate electrode of a MOS FET.  
   
   
       8 . The method according to  claim 7 , wherein the semiconductor layer is formed as a gate common to a PMOS FET and an NMOS FET adjacent to each other, and the (p+n)-type impurity layer is formed in a region corresponding to a boundary between the PMOS FET and the NMOS FET.  
   
   
       9 . The method according to  claim 1 , wherein the (p+n)-type impurity layer is formed so that the total concentration of the p-type impurity and the n-type impurity is 5E20 cm −3  or less.  
   
   
       10 . A method of manufacturing a semiconductor device including forming a silicide film on a surface of a semiconductor layer, the method comprising: 
 forming in the semiconductor layer a p-type impurity layer, an n-type impurity layer and a (p+n)-type impurity layer between the n-type and p-type impurity layers by introducing impurities;    forming an impurity segregation layer on the n-type and p-type impurity layers and the (p+n)-type impurity layer by heat-treating the semiconductor layer;    removing an oxide film on the impurity segregation layer;    introducing an impurity into the impurity segregation layer; and    thereafter forming the silicide film by forming a film of a metallic material on the impurity segregation layer and by heat-treating the film of the metallic material.    
   
   
       11 . The method according to  claim 10 , wherein the n-type and p-type impurity layers and the (p+n)-type impurity layer are formed by covering the surface of the semiconductor layer on one side with a first mask, introducing one of the p-type and n-type impurities into a first exposed portion, covering the surface of the semiconductor layer on the other side with a second mask, and introducing the other impurity into a second exposed portion including a doubly exposed portion which is also included in the first exposed portion.  
   
   
       12 . The method according to  claim 10 , wherein polycrystalline Si or polycrystalline SiGe is used as the semiconductor layer.  
   
   
       13 . The method according to  claim 10 , wherein a layer of a compound of the p-type impurity and the n-type impurity is caused to segregate as the impurity segregation layer on the (p+n)-type impurity layer.  
   
   
       14 . The method according to  claim 13 , wherein one of As—B, P—B and As—B—P is caused to segregate as the compound layer.  
   
   
       15 . The method according to  claim 10 , wherein Ni or a compound of Ni and at least one of Pd, Pt and Co is used as the metallic material.  
   
   
       16 . The method according to  claim 10 , wherein the semiconductor layer is formed as a gate electrode of a MOS FET.  
   
   
       17 . The method according to  claim 16 , wherein the semiconductor layer is formed as a gate common to a PMOS FET and an NMOS FET adjacent to each other, and the (p+n)-type impurity layer is formed in a region corresponding to a boundary between the PMOS FET and the NMOS FET.  
   
   
       18 . The method according to  claim 10 , wherein the (p+n)-type impurity layer is formed so that the total concentration of the p-type impurity and the n-type impurity is 5E20 cm −3  or less.  
   
   
       19 . Wiring formed by a suicide layer formed on a semiconductor layer which has at least one of a p-type impurity portion into which a p-type impurity is introduced and an n-type impurity portion into which an n-type impurity is introduced, and a (p+n)-type impurity portion into which the p-type and n-type impurities are introduced, wherein the total concentration of the p-type impurity and the n-type impurity contained in the (p+n)-type impurity portion is 5E20 cm −3  or less in the (p+n)-type impurity portion.  
   
   
       20 . A semiconductor device comprising: 
 a PMOS FET;    an NMOS FET; and    wiring provided as a gate electrode formed in common to the PMOS FET and the NMOS FET, the wiring being formed by a silicide layer formed on the a semiconductor layer, the semiconductor layer having:    a p-type impurity portion into which a p-type impurity is introduced;    an n-type impurity portion into which an n-type impurity is introduced; and    a (p+n)-type impurity portion into which the p-type and n-type impurities are introduced,    wherein the total concentration of the p-type impurity and the n-type impurity contained in the (p+n)-type impurity portion is 5E20 cm −3  or less in the (p+n)-type impurity portion.