Semiconductor device and manufacturing method thereof

Abstract

A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).

1 - 19 . (canceled)  
     
     
         20 . A manufacturing method of a semiconductor device comprising: 
 forming on a semiconductor layer a fin-shaped semiconductor layer which is long in a first direction and short in a second direction crossing the first direction;    forming a dummy gate insulating layer on side surfaces of the semiconductor layer in the second direction;    forming a dummy gate electrode adjacent to the dummy gate insulating layer;    forming a source/drain extension area and a source/drain area in the semiconductor layer;    forming an insulating layer which covers the semiconductor layer;    exposing surfaces of the dummy gate insulating layer and the dummy gate electrode by polishing or etching the insulating layer;    removing the dummy gate insulating layer and the dummy gate electrode;    oxidizing the semiconductor layer at a part where the dummy gate insulating layer had been formed, and forming an oxide layer there;    removing the oxide layer;    forming a gate insulating layer at a part where the dummy gate insulating layer had been formed; and    forming a gate electrode adjacent to the gate insulating layer.    
     
     
         21 . A manufacturing method of the semiconductor device comprising: 
 forming on a semiconductor substrate a plurality of fin-shaped first semiconductor layers which are long in a first direction and short in a second direction crossing the first direction, and a second semiconductor layer which connects end portions of a plurality of the first semiconductor layer in the first direction with each other;    forming a dummy gate insulating layer on side surfaces of each of a plurality of the first semiconductor layers in the second direction;    forming a dummy gate electrode adjacent to the dummy gate insulating layer;    forming a source/drain extension area in each of a plurality of the first semiconductor layers;    forming a source/drain area in the second semiconductor layer;    forming an insulating layer which covers the first and second semiconductor layers;    exposing surfaces of the dummy gate insulating layer and the dummy gate electrode by polishing or etching the insulating layer;    removing the dummy gate insulating layer and the dummy gate electrode;    oxidizing the first semiconductor layer at a part where the dummy gate insulating layer had been formed, and forming an oxide layer there;    removing the oxide layer;    forming a gate insulating layer at a part where the dummy gate insulating layer had been formed; and    forming a gate electrode adjacent to the gate insulating layer.    
     
     
         22 . A manufacturing method of a semiconductor device comprising: 
 forming a cap insulating layer on a semiconductor layer on a first insulating layer;    etching the semiconductor layer by using the cap insulating layer as a mask, and making the semiconductor layer into a fin shape which is long in a first direction and short in a second direction crossing the first direction;    forming a second insulating layer which covers the semiconductor layer;    exposing a surface of the cap insulating layer by polishing or etching the second insulating layer;    reducing a size of the cap insulating layer by etching the cap insulating layer based on isotropic etching;    forming on the semiconductor layer a first resist having a slit whose width is smaller than a width of the semiconductor layer in the first direction;    making a width of the semiconductor layer at a central portion in the second direction smaller than a width of the semiconductor layer at an end portion in the first direction by etching the semiconductor layer with the cap insulating layer and the first resist being used as masks;    forming a source/drain extension area at the central portion of the semiconductor layer; and    forming a source/drain area at the end portion of the semiconductor layer in the first direction.    
     
     
         23 . The manufacturing method according to  claim 22 , further comprising: 
 further reducing a size of the cap insulating layer by again etching the cap insulating layer based on the isotropic etching after etching the semiconductor layer with the cap insulating layer and the resist being used as the masks and before forming the source/drain extension area; forming on the semiconductor layer a second resist having a slit whose width is smaller than a width of the slit of the first resist in the first direction; and    making the width of the semiconductor layer at the central portion in the second direction smaller than the width of the semiconductor layer at the central portion in the second direction by etching the semiconductor layer with the cap insulating layer and the second resist being used as masks.    
     
     
         24 . A manufacturing method of semiconductor device comprising: 
 forming on a semiconductor layer a fin-shaped semiconductor layer which is long in a first direction and short in a second direction crossing the first direction;    forming a gate insulating layer on side surfaces of the semiconductor layer in the second direction;    forming a gate electrode adjacent to the gate insulating layer;    forming a source/drain extension area in the semiconductor layer by tilted ion implantation;    forming a sidewall insulating layer on a sidewall of the gate electrode;    forming a source/drain area by combination of tilted ion implantation and vertical ion implantation, or vertical ion implantation; and    forming a silicide layer on the gate electrode and a surface of the source/drain area, wherein conditions of silicidation are set in such a manner the silicide layer is not formed in the entire inner portion of the semiconductor layer in the source/drain area.    
     
     
         25 . A manufacturing method of a semiconductor device comprising: 
 forming on a semiconductor substrate a fin-shaped first semiconductor layer which is long in a first direction and short in a second direction crossing the first direction, a silicidation stopper on the first semiconductor layer, and a second semiconductor layer on the silicidation stopper;    forming a gate insulating layer on side surfaces of the first semiconductor layer in the second direction;    forming a gate electrode adjacent to the gate insulating layer;    forming a source/drain extension area in the first semiconductor layer;    forming a sidewall insulating layer on sidewalls of the gate electrode;    growing an epitaxial layer on surfaces of the first and second semiconductor layers by a selective growth, and coupling the epitaxial layer from the first semiconductor layer with the epitaxial layer from the second semiconductor layer;    forming a source/drain area in the first semiconductor layer; and    forming a silicide layer on the gate electrode, the second semiconductor layer and the epitaxial layer,    wherein the silicidation stopper functions as a stopper in silicidation in such a manner that silicidation does not proceed from an upper portion of the first semiconductor layer in silicidation.    
     
     
         26 - 27 . (canceled)  
     
     
         28 . The manufacturing method according to  claim 20 , wherein the source/drain extension area is formed by an inclined ion implantation.  
     
     
         29 . The manufacturing method according to  claim 20 , wherein the source/drain extension area is formed by a combination of an inclined ion implantation and a vertical ion implantation, or a vertical ion implantation.  
     
     
         30 . The manufacturing method according to  claim 20 , wherein after forming the source/drain extension area, a side wall insulating layer is formed on a side wall of the gate electrode before forming the source/drain area.  
     
     
         31 . The manufacturing method according to  claim 20 , wherein a width of the semiconductor layer in the channel area adjacent to the gate insulating layer in the second direction is controlled based on a thickness of the oxide layer.  
     
     
         32 . The manufacturing method according to  claim 20 , wherein polishing or etching of the insulating layer is executed with a cap insulating layer formed on the semiconductor layer being used as a stopper.  
     
     
         33 . The manufacturing method according to  claim 20 , wherein polishing or etching of the insulating layer is executed with the dummy gate electrode being used as a stopper.  
     
     
         34 . The manufacturing method according to  claim 20 , further comprising forming a silicide layer on the gate electrode and the source/drain area.  
     
     
         35 . The manufacturing method according to  claim 21 , wherein the source/drain extension area is formed by an inclined ion implantation.  
     
     
         36 . The manufacturing method according to  claim 21 , wherein the source/drain extension area is formed by a combination of an inclined ion implantation and a vertical ion implantation, or a vertical ion implantation.  
     
     
         37 . The manufacturing method according to  claim 23 , wherein the central portion of the semiconductor layer is a channel area.  
     
     
         38 . The manufacturing method according to  claim 24 , further comprising growing an epitaxial layer on a surface of the semiconductor layer by a selective growth after forming the side wall insulating layer and before forming the source/drain area.  
     
     
         39 . The manufacturing method according to  claim 24 , wherein the epitaxial layer becomes a part of the source/drain area, and also becomes a semiconductor which is consumed in the silicidation.  
     
     
         40 . The manufacturing method according to  claim 24 , wherein the epitaxial layer is formed on a top face and side surfaces of the semiconductor layer.  
     
     
         41 . The manufacturing method according to  claim 25 , wherein the silicidation stopper is comprised by a silicon oxide or a silicon nitride.