1T-nmemory cell structure and its method of formation and operation

Abstract

A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

1 - 25 . (canceled)  
     
     
         26 . A memory device comprising: 
 a plurality of memory slices, each memory slice comprising a plurality of memory cells arranged vertically and horizontally in a plane and which are commonly electrically coupled to a respective sense line interconnect; and    a plurality of access transistors, each electrically coupled to a respective sense line interconnect of a memory slice, each access transistor operating during a read operation to couple a selected memory cell in a slice to a sense amplifier.    
     
     
         27 . The memory device of  claim 26 , wherein each of said memory cells is a programmable conductor random access memory cell.  
     
     
         28 . The memory device of  claim 26 , wherein each of said memory cells is a ferroelectric random access memory cell.  
     
     
         29 . The memory device of  claim 26 , wherein each of said memory cells is a polymer memory cell.  
     
     
         30 . The memory device of  claim 26 , wherein each of said memory cells is a phase-changing chalcogenide memory cell.  
     
     
         31 . The memory device of  claim 26 , wherein each memory cell has an associated read line.  
     
     
         32 . The memory device of  claim 31 , wherein during a read operation said read line is selected by a row decoder, said access transistor is selected by a column decoder.  
     
     
         33 . A memory device comprising: 
 a plurality of access transistors each adapted to be electrically coupled with a sense amplifier;    a plurality of memory slices, each memory slice comprising a stacked plurality of columns of commonly electrically coupled memory cells, each column of commonly electrically coupled memory cells being electrically coupled to a respective sense line wherein each of said memory cells is a programmable conductor random access memory cell; and    a plurality of sense line interconnects, each said sense line interconnect being electrically coupled between a respective access transistor and the sense lines of a respective memory slice.    
     
     
         34 . The memory device of  claim 33 , further comprising: 
 a plurality of sensing circuits, each said sensing circuit coupling to said respective access transistor.    
     
     
         35 . The memory device of  claim 33 , further comprising a plurality of read lines respectfully associated with said memory cells for selecting an associated memory cell for a read operation.  
     
     
         36 - 76 . (canceled)  
     
     
         77 . A computer system comprising: 
 a central processing unit; and    a memory device electrically coupled to said central processing unit, said memory device comprising:    a plurality of memory slices, each memory slice comprising a plurality of memory cells arranged vertically and horizontally in a plane and which are commonly electrically coupled to a respective sense line interconnect, wherein each of said memory cells is a programmable conductor random access memory cell; and    a plurality of access transistors, each electrically coupled to a respective sense line interconnect of a memory slice, each access transistor operating during a read operation to couple a selected memory cell in a slice to a sense amplifier.    
     
     
         78 . The computer system of  claim 77 , wherein each memory cell has an associated read line.  
     
     
         79 . The computer system of  claim 78 , wherein during a read operation said read line is selected by a row decoder, said access transistor is selected by a column decoder.  
     
     
         80 . A computer system comprising: 
 a central processing unit; and    a memory device electrically coupled to said central processing unit, said computer system comprising:    a plurality of access transistors each adapted to be electrically coupled with a sense amplifier;    a plurality of memory slices, each memory slice comprising a stacked plurality of columns of commonly electrically coupled memory cells, each column of commonly electrically coupled memory cells being electrically coupled to a respective sense line; and    a plurality of sense line interconnects, each said sense line interconnect being electrically coupled between a respective access transistor and the sense lines of a respective memory slice.    
     
     
         81 . The computer system of  claim 80 , further comprising: 
 a plurality of sensing circuits, each said sensing circuit coupling to said respective access transistor.    
     
     
         82 . The computer system of  claim 81 , further comprising a plurality of read lines respectfully associated with said memory cells for selecting an associated memory cell for a read operation.  
     
     
         83 . The computer system of  claim 80 , wherein each of said memory cells is a phase changing chalcogenide memory cell.  
     
     
         84 . The computer system of  claim 80 , wherein each of said memory cells is a polymer memory cell.  
     
     
         85 . The computer system of  claim 80 , wherein each of said memory cells is a programmable conductor random access memory cell.  
     
     
         86 . The computer system of  claim 80 , wherein each of said memory cells is a ferroelectric random access memory cell.