US2006176067A1PendingUtilityA1

Method and system for detecting potential reliability failures of integrated circuit

Assignee: TAIWAN SEMICONDUCTOR MFGPriority: May 7, 2004Filed: Apr 17, 2006Published: Aug 10, 2006
Est. expiryMay 7, 2024(expired)· nominal 20-yr term from priority
G11C 29/025G11C 29/02
31
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Claims

Abstract

A method and system for detecting a potential reliability problem cause by electrical bridging in an integrated circuit. A voltage difference is created between two conducting lines in the integrated circuit to accelerate the bridging effect for a predetermined period of time. The conducting lines are detected to determine whether an undesired connection has occurred due to the bridging effect between the conducting lines.

Claims

exact text as granted — not AI-modified
1 . A method for detecting a potential bridging effect between a first conducting line and a second conducting line in an integrated circuit, the method comprising: 
 creating a voltage difference between the first conducting line and the second conducting line for a predetermined period of time for inducing the bridging effect therebetween; and    detecting whether an undesired connection has occurred due to the bridging effect between the first conducting line and the second conducting line.    
   
   
       2 . The method of  claim 1  wherein the first conducting line is adjacent to the second conducting line.  
   
   
       3 . The method of  claim 1  wherein the first conducting line and the second conducting line are made of metal or silicon-based materials.  
   
   
       4 . The method of  claim 1  wherein the creating a voltage difference further comprises: 
 applying a first voltage to the first conducting line; and    applying a second voltage to the second conducting line wherein the first voltage is higher than the second voltage.    
   
   
       5 . The method of  claim 1  wherein: 
 the first conducting line is adjacent to the second conducting line;    the first conducting line and the second conducting line are made of metal or silicon-based materials; and    the step of creating a voltage difference further comprises:    applying a first voltage to the first conducting line; and    applying a second voltage to the second conducting line wherein the first voltage is higher than the second voltage.    
   
   
       6 . A system for detecting a potential bridging effect between a first conducting line and a second conducting line in an integrated circuit, the system comprising: 
 means for creating a voltage difference between the first conducting line and the second conducting line for a predetermined period of time for inducing the bridging effect therebetween; and    means for detecting whether a connection has occurred due to the bridging effect between the first conducting line and the second conducting line.    
   
   
       7 . The system of  claim 6  wherein the first conducting line is adjacent to the second conducting line.  
   
   
       8 . The system of  claim 7  wherein the integrated circuit is a memory chip.  
   
   
       9 . The system of  claim 8  wherein the means for creating a voltage difference further comprises a selection circuit for selectively raising the first conducting line or the second conducting line to a high voltage level.  
   
   
       10 . The system of  claim 9  wherein the selection circuit selects the first conducting line or the second conducting line in response to inputs designating an address of a memory cell and an activation of a data erasure.  
   
   
       11 . The system of  claim 10  wherein the selection circuit is further responsive to an input designating the predetermined period of time.  
   
   
       12 . The system of  claim 6  wherein the integrated circuit is a memory chip.  
   
   
       13 . The system of  claim 6  wherein the means for creating a voltage difference further comprises a selection circuit for selectively raising the first conducting line or the second conducting line to a high voltage level.  
   
   
       14 . The system of  claim 13  wherein the selection circuit selects the first conducting line or the second conducting line in response to inputs designating an address of a memory cell and an activation of a data erasure.  
   
   
       15 . The system of  claim 13  wherein the selection circuit is further responsive to an input designating the predetermined period of time.

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