US2006177983A1PendingUtilityA1

Method for forming a notched gate

46
Individually held — no corporate assignee on recordPriority: Jun 20, 2002Filed: Mar 31, 2006Published: Aug 10, 2006
Est. expiryJun 20, 2022(expired)· nominal 20-yr term from priority
Inventors:Jigish Trivedi
H10D 64/01336H10D 64/01324H10D 64/518H10D 64/017H10D 30/0227H10D 30/601
46
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Claims

Abstract

Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a substrate. The dummy gate is etched to form notches in the dummy gate, and sidewall spacers are formed on the sidewalls of the notched dummy gate. The dummy gate is removed, and a notched gate is formed. The methods allow the height and depth of the notches to be independently controlled, and transistors having shorter channel lengths are formed.

Claims

exact text as granted — not AI-modified
1 . A method of forming a notched gate comprising: 
 supplying a substrate;    forming a dummy gate on said substrate, said dummy gate having sidewalls;    etching said dummy gate to form laterally recessed notches in said dummy gate;    forming sidewall spacers on said sidewalls of said dummy gate;    depositing a layer of dielectric material over said dummy gate;    removing the dielectric material overlying said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers;    forming a gate oxide in said recess; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       2 . The method of  claim 1 , further comprising: 
 forming a well region in said substrate;    forming at least one isolation region in said substrate;    forming extensions regions in said well region after etching said dummy gate, said extension regions formed within said well region adjacent to said dummy gate; and    forming doping regions in said well region adjacent to said sidewall spacers.    
   
   
       3 . The method of  claim 2 , wherein said dummy gate is formed on said substrate over said well region.  
   
   
       4 . The method of  claim 2 , further comprising: 
 providing at least one pocket implant within said well region under said extension regions.    
   
   
       5 . The method of  claim 2 , wherein said at least one isolation region comprises an isolation trench.  
   
   
       6 . The method of  claim 2 , wherein said doped regions and said extension regions comprise source/drain regions.  
   
   
       7 . The method of  claim 1 , wherein said dummy gate comprises at least one layer.  
   
   
       8 . The method of  claim 1 , wherein said dummy gate comprises: 
 a first layer proximate to said substrate, wherein said first layer comprises a first dielectric layer;    a second layer proximate to said first layer; and    a third layer proximate to said second layer.    
   
   
       9 . The method of  claim 8 , wherein thickness of said second layer comprises the height of said laterally recessed notches.  
   
   
       10 . The method of  claim 9 , wherein said height of said laterally recessed notches is in a range of about 100 to about 500 Å.  
   
   
       11 . A method of forming a notched gate comprising: 
 supplying a substrate;    forming a well region in said substrate;    forming at least one isolation region in said substrate;    forming a dummy gate on said substrate over said well region, said dummy gate having sidewalls;    etching said dummy gate to form laterally recessed notches in said dummy gate;    forming extension regions in said well region after etching said dummy gate, said extension regions formed within said well region adjacent to said dummy gate;    forming sidewall spacers on said sidewalls of said dummy gate;    forming doped regions in said well region adjacent to said sidewall spacers;    depositing a layer of dielectric material over said dummy gate;    removing the dielectric material overlying said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers;    forming a gate oxide in said recess; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       12 . The method as claimed in  claim 11  further comprising providing at least one pocket implant within said well region under said extension regions.  
   
   
       13 . The method as claimed in  claim 11  wherein said at least one isolation region comprises an isolation trench.  
   
   
       14 . The method as claimed in  claim 11  wherein said layer of dielectric material is formed by depositing an inter-layer dielectric material over said substrate and said dummy gate.  
   
   
       15 . The method as claimed in  claim 11  wherein said doped regions and said extension regions comprise source/drain regions.  
   
   
       16 . A method of forming a notched gate comprising: 
 supplying a substrate;    forming a dummy gate on said substrate, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer;    etching one of said at least one layers to form laterally recessed notches in said dummy gate;    forming sidewall spacers on said sidewalls of said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers;    forming a gate oxide in said recess; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       17 . The method of  claim 16 , further comprising: 
 depositing a layer of dielectric material over said dummy gate; and    removing the dielectric material overlaying said dummy gate.    
   
   
       18 . The method of  claim 17 , wherein said layer of dielectric material is formed by depositing an inter-layer dielectric material over said substrate and said dummy gate.  
   
   
       19 . A method of forming a notched gate comprising: 
 supplying a substrate;    forming a dummy gate on said substrate, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer;    etching one of said at least one layers to form laterally recessed notches in said dummy gate;    forming sidewall spacers on said sidewalls of said dummy gate;    depositing a layer of dielectric material over said dummy gate;    removing the dielectric material overlying said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers;    forming a gate oxide in said recess; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       20 . A method of forming a notched gate comprising: 
 supplying a substrate;    forming a well region in said substrate;    forming at least one isolation region in said substrate;    forming a dummy gate on said substrate over said well region, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer;    etching one of said at least one layers to form laterally recessed notches in said dummy gate;    forming extension regions in said well region after etching said dummy gate, said extension regions formed within said well region adjacent to said dummy gate;    forming sidewall spacers on said sidewalls of said dummy gate;    forming doped regions in said well region adjacent to said sidewall spacers;    depositing a layer of dielectric material over said dummy gate;    removing the dielectric material overlying said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers;    forming a gate oxide in said recess; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       21 . A method of controlling the notch dimensions of a damascene notched gate comprising: 
 forming a dummy gate over a substrate, said dummy gate having sidewalls;    etching said dummy gate to form laterally recessed notches in said dummy gate, wherein said etch is controlled to select the depth of said laterally recessed notches;    forming sidewall spacers on said sidewalls of said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       22 . The method as claimed in  claim 21  wherein said depth is in the range of about 50 to about 200 Å.  
   
   
       23 . A method of controlling the notch dimensions of a damascene notched gate comprising: 
 forming a dummy gate over a substrate, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer having a selected thickness;    etching said dummy gate to form laterally recessed notches in said dummy gate, wherein said etch is controlled to select the depth of said laterally recessed notches, and wherein the height of said laterally recessed notches is determined by said selected thickness of one of said at least one layers;    forming sidewall spacers on said sidewalls of said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       24 . The method as claimed in  claim 23  wherein said height is in the range of about 100 to about 500 Å.  
   
   
       25 . The method as claimed in  claim 23  wherein said height is in the range of about 100 to about 500 Å and said depth is in the range of about 50 to about 200 Å.  
   
   
       26 . A method of forming a notched gate comprising: 
 supplying a substrate;    forming a dummy gate on said substrate, said dummy gate having sidewalls, wherein said dummy gate comprises: 
 a first layer proximate to said substrate, wherein said first layer comprises a first dielectric layer;  
 a second layer proximate to said first layer; and  
 a third layer proximate to said second layer;  
   etching said second layer to form laterally recessed notches in said dummy gate;    forming sidewall spacers on said sidewalls of said dummy gate;    depositing a layer of dielectric material over said dummy gate;    removing the dielectric material overlying said dummy gate;    removing said dummy gate to form a recess between said sidewall spacers;    forming a gate oxide in said recess; and    depositing a permanent gate material in said recess to form a notched gate.    
   
   
       27 . The method as claimed in  claim 26  wherein said step of etching said second layer comprises a wet etch, and wherein said first dielectric layer is selected to be resistant to said-wet etch.  
   
   
       28 . The method as claimed in  claim 26  wherein said first dielectric layer is selected from gate oxide, silicon nitride, aluminum oxide, silicon carbide, hafnium oxide, and combinations thereof.

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