Three-dimensional memory structure and manufacturing method thereof

Abstract

A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.

1 . A memory structure, comprising: 
 a first conductor;    a second conductor cross over the first conductor;    a third conductor cross over the second conductor;    a first diode between the first conductor and the second conductor;    a second diode between the second conductor and the third conductor, wherein the directions of currents flowing through the first diode and second diode are opposite;    a first anti-fuse between the first conductor and the second conductor; and    a second anti-fuse between the second conductor and the third conductor.    
   
   
       2 . The memory structure of  claim 1 , wherein the first anti-fuse is between the first conductor and the first diode.  
   
   
       3 . The memory structure of  claim 1 , wherein the first anti-fuse is between the first diode and second conductor.  
   
   
       4 . The memory structure of  claim 1 , wherein the first anti-fuse is within the first diode.  
   
   
       5 . The memory structure of  claim 1 , wherein the first anti-fuse and the second anti-fuse comprise oxide.  
   
   
       6 . A memory structure, comprising: 
 a first conductor;    a second conductor cross over the first conductor;    a third conductor cross over the second conductor;    a first layer of a first conductivity between the first conductor and the second conductor, a second layer of the first conductivity between the second conductor and the third conductor;    a third layer of a second conductivity between the first layer and the second conductor;    a fourth layer of the second conductivity between the second conductor and the second layer;    a first anti-fuse between the first conductor and the second conductor; and    a second anti-fuse between the second conductor and the third conductor.    
   
   
       7 . The memory structure of  claim 6 , wherein the first anti-fuse is between the first conductor and the first layer.  
   
   
       8 . The memory structure of  claim 6 , wherein the first anti-fuse is between the first layer and the second conductor.  
   
   
       9 . The memory structure of  claim 6 , wherein the first anti-fuse is between the first layer and the first layer of the second conductivity.  
   
   
       10 . The memory structure of  claim 9 , wherein the first conductivity comprises n type.  
   
   
       11 . The memory structure of  claim 9 , wherein the second conductivity comprises p type.  
   
   
       12 . The memory structure of  claim 9 , wherein the first conductivity comprises p type.  
   
   
       13 . The memory structure of  claim 9 , wherein the second conductivity comprises n type.  
   
   
       14 . The memory structure of  claim 9 , wherein the first anti-fuse and the second anti-fuse comprise oxide.