Phase change memory device

Abstract

A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.

1 . A phase change memory device comprising: 
 a substrate;    a plurality of cell arrays stacked above said substrate and each including a matrix layout of a plurality of memory cells, each said memory cell storing therein as data a resistance value determinable by a phase change;    a write circuit configured to write a pair cell constituted by two neighboring memory cells within said plurality of cell arrays in such a manner as to write one of said pair cell into a high resistance value state and write the other into a low resistance value state; and    a read circuit configured to read complementary resistance value states of said pair cell as a one bit of data.    
     
     
         2 . The phase change memory device according to  claim 1 , wherein 
 each said cell array has a plurality of mutually parallel first wiring lines and a plurality of second wiring lines disposed to cross said first wiring lines while being insulatively isolated from said first wiring lines, and wherein    each said memory cell has a chalcogenide and a diode being stacked at each cross portion of said first wiring lines and said second wiring lines.    
     
     
         3 . The phase change memory device according to  claim 2 , wherein 
 said diode of said memory cell is a Schottky diode formed of a lamination film of a semiconductor film and a metal film.    
     
     
         4 . The phase change memory device according to  claim 2 , wherein 
 upper and lower neighboring cell arrays share at least one group of said first wiring lines and said second wiring lines.    
     
     
         5 . The phase change memory device according to  claim 2 , wherein 
 upper and lower neighboring cell arrays share at least one group of said first wiring lines and said second wiring lines, and wherein    said upper and lower neighboring cell arrays are opposite to each other in lamination order of said chalcogenide and diode.    
     
     
         6 . The phase change memory device according to  claim 2 , wherein 
 said first wiring lines and second wiring lines are potentially fixed to cause said of each memory cell to become reverse-biased during non-selection, and wherein    during data reading or writing, a first wiring line and a second wiring line which are presently selected are pulse-driven to permit a diode of a memory cell being selected by these wiring lines to become forward-biased.    
     
     
         7 . The phase change memory device according to  claim 2 , wherein 
 said diode of said memory cell is connected in series to said chalcogenide while having a polarity with said first wiring line side as a cathode and with said second wiring line side as an anode, and further comprising    a selector circuit for holding said first wiring lines in a higher potential state than said second wiring lines during non-selection and for supplying a negative logic pulse and a positive logic pulse to said first wiring line and second wiring line which are selected during data reading or writing, respectively.    
     
     
         8 . The phase change memory device according to  claim 2 , wherein 
 said pair cell is made up of two upper and lower neighboring memory cells between upper and lower neighboring cell arrays sharing said second wiring lines.    
     
     
         9 . The phase change memory device according to  claim 2 , wherein 
 said pair cell is made up of two neighboring memory cells in each cell array which share one of said second wiring lines and which are connected to different first wiring lines.    
     
     
         10 . The phase change memory device according to  claim 1 , wherein 
 said read circuit has a differential sense amplifier circuit operable to detect a difference of cell current between two memory cells making up said pair cell.    
     
     
         11 . The phase change memory device according to  claim 4 , wherein 
 said write circuit is configured to be operatively associated with a plurality of neighboring memory cells to be selected from said plurality of cell arrays, for supplying a negative logic write pulse to a selected first wiring line and supplying a positive logic write pulse to a selected second wiring line while adjusting an overlap time of these pulses in accordance with data to be written.    
     
     
         12 . The phase change memory device according to  claim 11 , wherein 
 said write circuit comprises:    a pulse generator circuit configured to generate two types of pulses being the same in pulse width as each other and having a phase difference therebetween;    a logic gate circuit configured to output a negative logic pulse being given to one of said first and second wiring lines and a positive logic pulse being given to the other with an overlap time thereof determined by a combination logic depending upon write data of the two types of pulses as output from said pulse generator circuit; and    a pulse booster circuit for boosting at least one of said negative logic pulse and said positive logic pulse output from said logic gate circuit when the write data is in a high resistance value state so as to generate said negative logic write pulse and said positive logic write pulse.    
     
     
         13 . The phase change memory device according to  claim 1 , wherein 
 said plurality of cell arrays comprise:    a first cell array being formed above said substrate and having a plurality of mutually parallel first bit lines, a plurality of memory cells laid out on each first bit line at a prespecified pitch, and a plurality of first word lines laid out on said memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said first bit lines;    a second cell array being formed above said first cell array while sharing said first word lines with said first cell array and having a plurality of memory cells arrayed in the same layout as said first cell array and a plurality of second bit lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said first word lines;    a third cell array being formed above said second cell array while sharing said second bit lines with said second cell array and having a plurality of memory cells laid out in the same layout as said second cell array and a plurality of second word lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said second bit lines; and    a fourth cell array being formed above said third cell array while sharing said second word lines with said third cell array and having a plurality of memory cells disposed in the same layout as the memory cells of said third cell array and a plurality of third bit lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said second word lines.    
     
     
         14 . The phase change memory device according to  claim 13 , wherein 
 the memory cell of each said cell array has a chalcogenide and a diode which are stacked at each corresponding cross portion of said first to third bit lines and said first and second word lines.    
     
     
         15 . The phase change memory device according to  claim 14 , wherein 
 said diode of each memory cell is a Schottky diode formed of a lamination film of a semiconductor film and a metal film.    
     
     
         16 . The phase change memory device according to  claim 14 , wherein 
 the lamination order of said chalcogenide and diode is inverse between upper and lower neighboring cell arrays, and said diode is formed to have a polarity with the side of said first to third bit lines as a cathode.    
     
     
         17 . The phase change memory device according to  claim 14 , wherein 
 every couple of upper and lower neighboring memory cells sharing one of said first word lines between said first cell array and said second cell array constitute a pair cell in which complementary data is stored, and wherein    every couple of upper and lower neighboring memory cells sharing one of said second word lines between said third cell array and said fourth cell array constitute a pair cell in which complementary data is stored.    
     
     
         18 . The phase change memory device according to  claim 14 , wherein 
 in each said first to fourth cell arrays, each two neighboring memory cells sharing said first and second word lines constitute a pair cell in which complementary data is stored.    
     
     
         19 . The phase change memory device according to  claim 16 , further comprising: 
 a selector circuit for holding said first to third bit lines in a lower potential state than said first and second word lines during non-selection and for supplying a negative logic pulse to at least one of said first to third bit lines and supplying a positive logic pulse to at least one of said first and second word lines during data reading or writing.    
     
     
         20 . The phase change memory device according to  claim 17 , wherein 
 said read circuit comprises a differential sense amplifier circuit with differential input terminals connected to a pair of bit lines which in turn are connected respectively to two memory cells as aligned in the lamination direction of said first to fourth cell arrays to thereby make up each pair cell, said differential sense amplifier circuit being operable to detect a cell current difference of such two memory cells.    
     
     
         21 . The phase change memory device according to  claim 18 , wherein 
 said read circuit comprises a differential sense amplifier circuit with differential input terminals connected to a pair of bit lines which in turn are connected respectively to two memory cells as lined within each of said first to fourth cell arrays to make up each pair cell, said differential sense amplifier being configured to detect a cell current difference of the two memory cells.    
     
     
         22 . The phase change memory device according to  claim 17 , wherein 
 said write circuit is configured to simultaneously perform writing operation with respect to four memory cells making up two pair cells which are aligned in the lamination direction of said first to fourth cell arrays, wherein said write circuit comprises:    a pulse generator circuit for generating two kinds of pulses being the same in pulse width as each other and having a phase difference therebetween;    a logic gate circuit for outputting a negative logic write pulse to be given to said first to third bit lines and a positive logic write pulse to be given to said first and second word lines, said negative logic write pulse and said positive logic write pulse having an overlap time determined by a combination logic of the two kinds of pulses depending upon write data; and    a pulse booster circuit for boosting at least one of said negative logic write pulse and said positive logic write pulse output from said logic gate circuit when the write data is in a high resistance value state.    
     
     
         23 . The phase change memory device according to  claim 18 , wherein 
 said write circuit is configured to perform in a time divisional manner a first simultaneous write operation with respect to four memory cells within four pair cells that are constituted within said first to fourth cell arrays respectively, said four memory cell being aligned in the lamination direction for writing a positive logic value, and a second simultaneous write operation with respect to the remaining four memory cells which are aligned in the lamination direction for writing a negative logic value, said write circuit comprising:    a pulse generator circuit for generating two kinds of pulses being the same in pulse width as each other and having a phase difference therebetween;    a logic gate circuit for outputting a negative logic write pulse to be given to said first to third bit lines and a positive logic write pulse to be given to the first and second word lines, said negative logic write pulse and said positive logic write pulse having an overlap time determined by a combination logic of the two kinds of pulses depending upon write data; and    a pulse booster circuit for boosting at least one of said negative logic write pulse and said positive logic write pulse output from said logic gate circuit when the write data is in a high resistance value state.    
     
     
         24 . The phase change memory device according to  claim 17 , wherein 
 said write circuit is configured to perform in a time divisional manner a first simultaneous write operation with respect to four memory cells of two pair cells constituted within said first and second cell arrays, each pair cell being constituted by upper and lower neighboring two memory cells, said two pair cells sharing said first wordline and being adjacently arranged in said first word line direction, and a second simultaneous write operation with respect to four memory cells of two pair cells constituted within said third and fourth cell arrays, each pair cell being constituted by upper and lower neighboring two memory cells, said two pair cells sharing said second wordline and being adjacently arranged in said second wordline direction, said write circuit comprising:    a pulse generator circuit for generating two kinds of pulses being the same in pulse width as each other and having a phase difference therebetween;    a logic gate circuit for outputting a positive logic write pulse to be given to a shared word line of upper and lower neighboring cell arrays and a negative logic write pulse to be given to two bit lines with said shared word line placed therebetween, said positive logic write pulse and said negative logic write pulse having an overlap time determined by a combination logic of said two kinds of pulses depending upon write data; and    a pulse booster circuit for boosting in a negative direction said negative logic write pulse to be output from said logic gate circuit when the write data is in a high resistance value state.    
     
     
         25 . The phase change memory device according to  claim 18 , wherein 
 said write circuit is configured to perform in a time divisional manner a first simultaneous write operation with respect to four memory cells of two pair cells that are constituted within said first and second cell arrays, respectively, to be upper and lower neighboring, and a second simultaneous write operation with respect to four memory cells of two pair cells that are constituted within said third and fourth cell arrays, respectively, to be upper and lower neighboring, said write circuit comprising:    a pulse generator circuit for generating two kinds of pulses being the same in pulse width as each other and having a phase difference therebetween;    a logic gate circuit for outputting a positive logic write pulse to be given to a shared word line of the upper and lower neighboring cell arrays and a negative logic write pulse to be given to two bit lines with said shared word line interposed therebetween, said positive logic write pulse and said negative logic write pulse having an overlap time determined by a combination logic of said two kinds of pulses depending upon write data; and    a pulse booster circuit for boosting in a negative direction said negative logic write pulse to be output from said logic gate circuit when the write data is in a high resistance value state.    
     
     
         26 . A method of fabricating a phase change memory device having a plurality of cell arrays in which a plurality of memory cells each of which stores therein as data a resistance value to be determined by a phase change are arranged in a matrix layout, wherein a fabrication process of each cell array comprising: 
 forming a plurality of mutually parallel first wiring lines on an underlying substrate;    forming above the substrate with said first wiring lines formed a lamination film of a chalcogenide layer and a semiconductor layer required for formation of a diode;    depositing a resist on said lamination film;    a first exposure step of exposing said resist by use of a mask as used at a lithography process for formation of said first wiring lines;    a second exposure step of again exposing said resist with said mask rotated by 90°;    developing said resist and then removing remainder part while permitting residence as a resist mask at double exposed portions or non-exposed portions in said first and second exposure steps;    etching said lamination film by use of said resist mask to form column-like memory cells as laid out in a matrix form;    burying an insulative dielectric film around said column-like memory cells; and    forming a plurality of second wiring lines in such a manner as to commonly connect together upper ends of said column-like memory cells lined in a direction orthogonally crossing said first wiring lines.