Method for manufacturing a semiconductor device and method for etching the same

Abstract

A method for manufacturing a semiconductor device with a dual damascene structure is comprising the steps of preparing a semiconductor substrate, forming a first wiring layer over said semiconductor substrate, forming an inorganic insulating film over said first wiring layer, forming a via hole in said inorganic insulating film by forming a first resist pattern with an opening on said inorganic insulating film and by etching said inorganic insulating film with said first resist pattern as an etching mask, eliminating said first resist pattern, forming an organic insulating film so that said organic insulting film covers an upper side of said inorganic insulating film and an interior of said via hole, forming a hard mask on said organic insulating film, forming a hard mask pattern by forming a second resist pattern with an opening on said hard mask and by etching said hard mask with said second resist pattern as an etching mask, forming a wiring groove by etching said organic insulating film with said second resist pattern and said hard mask pattern as etching masks until said organic insulating film inside said via hole is eliminated and simultaneously eliminating said second resist pattern, and implanting a conductive substance into said via hole and said wiring groove.

1 . A method for manufacturing a semiconductor device with a dual damascene structure, comprising the steps of: 
 preparing a semiconductor substrate;    forming a first wiring layer over said semiconductor substrate;    forming an inorganic insulating film over said first wiring layer;    forming a via hole in said inorganic insulating film by forming a first resist pattern with an opening on said inorganic insulating film and by etching said inorganic insulating film with said first resist pattern as an etching mask;    eliminating said first resist pattern;    forming an organic insulating film so that said organic insulting film covers an upper side of said inorganic insulating film and an interior of said via hole;    forming a hard mask on said organic insulating film;    forming a hard mask pattern by forming a second resist pattern with an opening on said hard mask and by etching said hard mask with said second resist pattern as an etching mask;    forming a wiring groove by etching said organic insulating film with said second resist pattern and said hard mask pattern as etching masks until said organic insulating film inside said via hole is eliminated and simultaneously eliminating said second resist pattern; and    implanting a conductive substance into said via hole and said wiring groove.    
   
   
       2 . The method according to  claim 1 , further comprising the steps of: 
 forming a diffusion barrier film on said first wiring layer after forming said first wiring layer over said semiconductor substrate, said inorganic insulating film being formed on said diffusion barrier film; and    eliminating a portion of said diffusion barrier film that is exposed at the bottom of said via hole after forming said wiring groove and simultaneously eliminating said second resist pattern.    
   
   
       3 . The method according to  claim 2 , wherein 
 said hard mask is comprised of a first hard mask and a second hard mask; and    said hard mask pattern is comprised of a first hard mask pattern and a second hard mask pattern.    
   
   
       4 . A method for manufacturing a semiconductor device with a dual damascene structure, comprising the steps of: 
 preparing a semiconductor substrate;    forming a first wiring layer over said semiconductor substrate;    forming an organic insulating film over said first wiring layer;    forming a via hole in said organic insulating film by forming a first resist pattern with an opening on said organic insulating film and by etching said organic insulating film with said first resist pattern as an etching mask and simultaneously eliminating said first resist pattern;    forming an inorganic insulating film so that said inorganic insulting film covers an upper side of said organic insulating film and an interior of said via hole;    forming a first hard mask and a second hard mask on said inorganic insulating film;    forming a first hard mask pattern and a second hard mask pattern by forming a second resist pattern with an opening on said second hard mask and by etching said first hard mask and said second hard mask with said second resist pattern as an etching mask;    eliminating said second resist pattern;    forming a wiring groove by etching said inorganic insulating film with said first hard mask pattern and said second hard mask pattern as etching masks until said inorganic insulating film inside said via hole is eliminated and simultaneously eliminating said second resist pattern; and    implanting a conductive substance into said via hole and said wiring groove.    
   
   
       5 . The method according to  claim 4 , further comprising the steps of: 
 forming a diffusion barrier film on said first wiring layer after forming said first wiring layer over said semiconductor substrate, said organic insulating film being formed on said diffusion barrier film; and    eliminating a portion of said diffusion barrier film that is exposed at the bottom of said via hole after forming said via hole in said organic insulating film and simultaneously eliminating said first resist pattern.    
   
   
       6 . The method according to  claim 1 , wherein said hard mask is a silicon dioxide film.  
   
   
       7 . The method according to  claim 1 , wherein said inorganic insulating film is a methyl-silsequioxane (MSQ) film.  
   
   
       8 . The method according to  claim 4 , wherein said inorganic insulating film is a methyl-silsequioxane (MSQ) film.  
   
   
       9 . The method according to  claim 1 , wherein said organic insulating film is a silicon low-k polymer film.  
   
   
       10 . The method according to  claim 4 , wherein said organic insulating film is a silicon low-k polymer film.  
   
   
       11 . The method according to  claim 1 , wherein said inorganic insulating film is methyl-silsequioxane (MSQ) film and said organic insulating film is a silicon low-k polymer film.  
   
   
       12 . The method according to  claim 4 , wherein said inorganic insulating film is methyl-silsequioxane (MSQ) film and said organic insulating film is a silicon low-k polymer film.  
   
   
       13 . The method according to  claim 2 , wherein said diffusion barrier film is a silicon nitride film.  
   
   
       14 . The method according to  claim 5 , wherein said diffusion barrier film is a silicon nitride film.  
   
   
       15 . The method according to  claim 3 , wherein said first hard mask is a silicon dioxide film, and said second hard mask is a silicon nitride film.  
   
   
       16 . The method according to  claim 4 , wherein said first hard mask is a silicon dioxide film, and said second hard mask is a silicon nitride film.  
   
   
       17 . The method according to  claim 3 , wherein said second hard mask is eliminated simultaneously with the elimination of said diffusion barrier film.  
   
   
       18 . The method according to  claim 5 , wherein a modified layer is formed by conducting a plasma treatment of a surface of said organic insulating film simultaneously with the elimination of said diffusion barrier film.  
   
   
       19 . A method for etching a dual damascene structure comprised of an inorganic insulating film, an organic insulating film, and a hard mask sequentially laminated over a first wiring layer, the method comprising the steps of: 
 forming a via hole in said inorganic insulating film by:    (a) forming said inorganic insulating film over said first wiring layer; and    (b) forming a first resist pattern with an opening on said inorganic insulating film and etching said inorganic insulating film with said first resist pattern as an etching mask;    forming a hard mask pattern by:    (a) eliminating said first resist pattern;    (b) forming said organic insulating film so that said organic insulating film covers a upper side of said inorganic insulating film and an inside of said via hole;    (c) forming said hard mask on said organic insulating film;    (d) forming a second resist pattern with an opening on said hard mask; and    (e) etching said hard mask with said second resist pattern as an etching mask; and    forming a wiring groove by etching said organic insulating film with said second resist pattern and said hard mask pattern as etching masks until said organic insulating film inside said via hole is eliminated and simultaneously eliminating said second resist pattern.    
   
   
       20 . The method according to  claim 19 , wherein said dual damascene structure further includes a diffusion barrier film formed on a first wiring layer; and 
 wherein said step of forming said inorganic insulating film over said first wiring layer includes forming said diffusion barrier on said first wiring layer, said inorganic insulating film being formed on said diffusion barrier film; and    further comprising a step of eliminating a portion of said diffusion barrier film that is exposed at the bottom of said via hole after forming a wiring groove and simultaneously eliminating said second resist pattern.    
   
   
       21 . The method according to  claim 20 , wherein 
 said hard mask is comprised of a first hard mask and a second hard mask; and    said hard mask pattern is comprised of a first hard mask pattern and a second hard mask pattern.    
   
   
       22 . The method according to  claim 21 , wherein said second hard mask pattern is eliminated simultaneously with the elimination of said diffusion barrier film.  
   
   
       23 . A method for etching a dual damascene structure comprising an organic insulating film, an inorganic insulating film, a first hard mask, and a second hard mask sequentially laminated over a first wiring layer, the method comprising the steps of: 
 forming a via hole in said organic insulating film by:    (a) forming said organic insulating film over said first wiring layer;    (b) forming a first resist pattern with an opening on said organic insulating film; and    (c) etching said organic insulating film with said first resist pattern as an etching mask;    while simultaneously etching said first resist pattern;    forming a first hard mask pattern and a second hard mask pattern by:    (a) forming said inorganic insulating film so that said inorganic insulating film covers an upper side of said organic insulating film and an inside of said via hole;    (b) forming a second resist pattern with an opening on said second hard mask, and;    (c) etching said first hard mask and said second hard mask with said second resist pattern as an etching mask; and    forming a wiring groove by:    (a) eliminating said second resist pattern; and    (b) etching said inorganic insulating film with said first hard mask pattern and said second hard mask pattern as etching masks until said inorganic insulating film inside said via hole is eliminated; and    while simultaneously eliminating said second hard mask pattern.    
   
   
       24 . The method according to  claim 23 , wherein said dual damascene structure further includes a diffusion barrier film formed on a first wiring layer; 
 wherein said step of forming said organic insulating film over said first wiring layer includes forming said diffusion barrier on said first wiring layer, said organic insulating film being formed on said diffusion barrier film; and    further comprising a step of eliminating a portion of said diffusion barrier film that is exposed at the bottom of said via hole after forming a via hole in said organic insulating film while simultaneously etching said first resist pattern.    
   
   
       25 . The method according to  claim 24 , wherein a modified layer is formed by conducting a plasma treatment of a surface of said organic insulating film simultaneously with the elimination of said diffusion barrier film.