Non-volatile memory and method of manufacturing the same

Abstract

A nonvolatile memory consisting of a substrate, a dielectric layer, word lines, word gates, conductive spacers, electron trapping layer, insulation layer and buried bit lines is provided. The dielectric layer is on the substrate and has several poly trenches thereon, and the word lines are disposed over the substrate across the poly trenches. The word gates are in the poly trenches between the word lines and the substrate, and the conductive spacers are between the word gates and the inner wall of each poly trench. The electron trapping layer is disposed between the conductive spacers and the inner wall of each poly trench and between the conductive spacers and the substrate. The insulation layer is between the conductive spacers and the word gates. The buried bit lines are in the substrate between the poly trenches.

1 . A non-volatile memory, comprising: 
 a substrate;    a dielectric layer on the substrate, wherein the dielectric layer comprises a plurality of trenches;    a plurality of word lines over the substrate, disposed across the trenches;    a plurality of word gates located in the trenches between the word lines and the substrate;    a plurality of conductive spacers located between the inner walls of the trenches and the word gates;    an electron trapping layer located between the conductive spacers and the inner walls of the trenches and between the conductive spacers and the substrate;    an insulating layer located between the conductive spacers and the word gates; and    a plurality of buried bit lines located in the substrate between the trenches.    
   
   
       2 . The non-volatile memory of  claim 1 , wherein further comprising an LDD area located in the substrate between the buried bit lines and the conductive spacers.  
   
   
       3 . The non-volatile memory of  claim 1 , wherein a material of the word lines comprises poly-silicon.  
   
   
       4 . The non-volatile memory of  claim 1 , wherein a material of the conductive spacers comprises poly-silicon.  
   
   
       5 . The non-volatile memory of  claim 1 , wherein the electron trapping layer comprises an ONO layer.  
   
   
       6 . The nonvolatile memory of  claim 1 , wherein a material of the word gates comprises poly-silicon.  
   
   
       7 . A manufacturing method of a non-volatile memory, comprising: 
 providing a substrate;    forming a plurality of dummy bit lines on the substrate;    forming an electron trapping layer covering the substrate and the dummy bit lines;    forming a plurality of conductive spacers on the sidewalls of the dummy bit lines;    forming a protection layer on the surface of the conductive spacers;    removing the electron trapping layer which is not covered by the conductive spacers;    forming a plurality of conductive layers between the dummy bit lines;    removing the dummy bit lines to form a plurality of strip structures;    performing a BL ion implantation process upon the substrate, so as to form a plurality of buried bit lines in the substrate;    covering a dielectric layer on the buried bit lines and exposing the top of the strip structures;    forming a plurality of word lines over the substrate, and the word lines are interlaced with the buried bit lines; and    etching the conductive layer in the strip structures by using the word lines as a mask to form a plurality of word gates.    
   
   
       8 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the step of forming the protection layer on the surface of the conductive spacers comprises using thermal oxidation method to form a thermal oxide layer on the surface of the conductive spacers.  
   
   
       9 . The manufacturing method of the non-volatile memory of  claim 8 , wherein keep a portion of the thermal oxide layer on the surface of the conductive spacers when removing the electron trapping layer.  
   
   
       10 . The manufacturing method of non-volatile memory of  claim 7 , wherein before forming the buried bit lines in the substrate, further comprises: 
 performing an LDD ion implantation process upon the substrate by using the strip structures as a mask to form a plurality of LDD areas in the substrate; and    forming a plurality of spacers on the sidewalls of the strip structures to serve as a mask of the BL ion implantation process.    
   
   
       11 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the step of forming the dummy bit lines on the substrate comprising: 
 growing a thin oxide layer on the substrate;    depositing a silicon nitride layer on the thin oxide layer; and    patterning the silicon nitride layer.    
   
   
       12 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the step of forming the conductive spacers on the sidewalls of the dummy bit lines comprising: 
 depositing a first poly-silicon layer on the substrate to cover the dummy bit lines; and    etching back the first poly-silicon layer to expose the electron trapping layer on top of the dummy bit lines.    
   
   
       13 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the step of forming a plurality of conductive layers between the dummy bit lines comprising: 
 depositing a second poly-silicon layer on the substrate to cover the dummy bit lines; and    planarizing the second poly-silicon layer with chemical mechanical polish to expose the top of the dummy bit lines.    
   
   
       14 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the step of forming the word lines interlacing with buried bit lines over the substrate comprising: 
 depositing a third poly-silicon layer over the substrate to cover the strip structures; and    patterning the third poly-silicon layer.    
   
   
       15 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the step of covering the dielectric layer on the buried bit lines comprising: 
 depositing a thin silicon nitride layer to serve as the polishing stop layer;    depositing an oxide dielectric layer on the substrate;    planarizing the oxidation dielectric layer with chemical mechanical polish and stopping on the thin silicon nitride layer; and    etching the silicon nitride layer to expose the top of the strip structures.    
   
   
       16 . The manufacturing method of the non-volatile memory of  claim 7 , wherein the method of removing the dummy bit lines comprises using hot phosphoric acid.