US2006220184A1PendingUtilityA1
Antireflective coating for use during the manufacture of a semiconductor device
Est. expirySep 24, 2023(expired)· nominal 20-yr term from priority
H10P 76/2043H10P 76/405H10P 50/285H10P 50/73H10W 20/081H10D 1/716H10B 12/033H10B 12/485H10B 12/312
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Claims
Abstract
An antireflective layer formed from boron-doped amorphous carbon may be removed using a process which is less likely to over etch a dielectric layer than conventional technology. This layer may be removed by exposing the layer to an oxygen plasma (i.e. an “ashing” process), preferably concurrently with the ashing and removal of an overlying photoresist layer. An inventive process which uses the inventive antireflective layer is also described.
Claims
exact text as granted — not AI-modified1 . An in-process semiconductor device, comprising:
an antireflective layer comprising amorphous carbon having a boron concentration of between about 0.1 atom % and about 20 atom %.
2 . The in-process semiconductor device of claim 1 further comprising the antireflective layer comprising amorphous carbon having a boron concentration of between about 0.1 atom % and about 10 atom %.
3 . The in-process semiconductor device of claim 1 further comprising the antireflective layer comprising amorphous carbon having a boron concentration of between about 1 atom % and about 15 atom %.
4 . The in-process semiconductor device of claim 1 further comprising the antireflective layer comprising amorphous carbon having a boron concentration of between about 5 atom % and about 10 atom %.
5 . The in-process semiconductor device of claim 1 further comprising a photoresist layer on the antireflective layer.
6 . The in-process semiconductor device of claim 5 further comprising:
a conductive contact location; and a dielectric layer having an opening therein, wherein the antireflective layer and the photoresist layer each have openings therein, wherein the openings in the dielectric layer, the antireflective layer, and the photoresist layer are aligned and expose the conductive contact location.
7 . The in-process semiconductor device of claim 6 wherein the conductive contact location is a conductive contact pad electrically coupled with a doped region within a semiconductor wafer.
8 . An antireflective layer used during the fabrication of an electronic device, comprising:
an antireflective layer comprising amorphous carbon having a boron concentration of between about 0.1 atom % and about 20 atom %.
9 . The antireflective layer of claim 8 wherein the antireflective layer is an etch mask.
10 . The antireflective layer of claim 9 further comprising the antireflective layer comprising amorphous carbon having a boron concentration of between about 0.1 atom % and about 10 atom %.
11 . The antireflective layer of claim 9 further comprising the antireflective layer comprising amorphous carbon having a boron concentration of between about 1 atom % and about 15 atom %.
12 . The antireflective layer of claim 9 further comprising the antireflective layer comprising amorphous carbon having a boron concentration of between about 5 atom % and about 10 atom %.
13 . The antireflective layer of claim 9 further comprising a photoresist layer on the antireflective layer.
14 . The antireflective layer of claim 13 further comprising:
a conductive contact location; and a dielectric layer having an opening therein, wherein the antireflective layer and the photoresist layer each have openings therein, wherein the openings in the dielectric layer, the antireflective layer, and the photoresist layer are aligned and expose the conductive contact location.
15 . The antireflective layer of claim 14 wherein the conductive contact location is a conductive contact pad electrically coupled with a doped region within a semiconductor wafer.
16 . The antireflective layer of claim 9 further having a thickness of between about 150 Å and about 500 Å.Join the waitlist — get patent alerts
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