US2006220243A1PendingUtilityA1
Electronic device package
Est. expiryFeb 1, 2021(expired)· nominal 20-yr term from priority
H10W 72/551H10W 74/00H10W 72/884H10W 72/865H10W 72/536H10W 90/754H10W 72/951H10W 72/075H10W 72/07337H10W 72/073H10W 72/354H10W 90/734H10W 90/701
46
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Claims
Abstract
An electronic device package comprises a substrate, a die, and a material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals (at a solder reflow temperature) for attaching the die to the substrate. In one embodiment, the package utilizes a material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals (at a solder reflow temperature) for attaching the die to the substrate. In an alternate embodiment, the package utilizes a material having a coefficient of thermal expansion α 2 of less than about 400 (four-hundred) ppm (parts per million)/° C. for attaching the die to the substrate. In another alternate embodiment, the package utilizes a rigid material for attaching the die to the substrate.
Claims
exact text as granted — not AI-modified1 . An electronic system package comprising:
a circuit board; a die; and a material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals at a solder reflow temperature of between about 200 degrees Centigrade and 280 degrees Centigrade, the material attaching the die to the circuit board.
2 . The electronic system package of claim 1 , wherein the circuit board comprises a flexible circuit board.
3 . The electronic system package of claim 1 , wherein the die comprises an integrated circuit fabricated on silicon.
4 . The electronic system package of claim 1 , wherein the die comprises one or more memory circuits.
5 . The electronic system package of claim 1 , wherein the die comprises one or more processor circuits.
6 . The electronic system package of claim 1 , wherein the die comprises one or more logic circuits.
7 . The electronic system package of claim 1 , wherein the die comprises one or more application specific integrated circuits.
8 . The electronic system package of claim 1 , wherein the material comprises a poly epoxide formed from one epoxide.
9 . The electronic system package of claim 1 , wherein the material comprises a poly epoxide formed from two or more epoxides.
10 . The electronic system package of claim 1 , wherein the material comprises a polyacrylate.
11 . The electronic system package of claim 1 , wherein the material comprises a polyolefin.
12 . The electronic system package of claim 1 , wherein the material comprises a polyimide.
13 . The electronic system package of claim 1 , wherein the material comprises a mixture of at least two of a poly epoxide, polyacrylate, polyimide, and polyolefin.
14 . The electronic system package of claim 1 , wherein the material comprises a copolymer of at least two of a poly epoxide, a polyacrylate, polyimide, and polyolefin.
15 . The electronic system package of claim 1 , wherein the material comprises a mixture of a poly epoxide and a polyimide.
16 . The electronic system package of claim 1 , wherein the material comprises a copolymer of a poly epoxide and a polyimide.
17 . The electronic system package of claim 1 , wherein the material has a Shore A hardness of greater than about 70.
18 . The electronic system package of claim 1 , wherein the material has a Shore D hardness of greater than about 20.
19 . An electronic system package, comprising:
a circuit board; a die; and a material having a coefficient of thermal expansion a2 of less than about 400 (four-hundred) ppm/° C. at a solder reflow temperature of about between about 200 degrees Centigrade and about 280 degrees Centigrade, the material attaching the die to the circuit board.
20 . The electronic system package of claim 19 , wherein the circuit board comprises a multi-metal layer circuit board.
21 . The electronic system package of claim 19 , wherein the die comprises gallium arsenide.
22 . The electronic system package of claim 19 , wherein the material comprises one or more polyimides.
23 . The electronic system package of claim 19 , wherein the die comprises one or more memory circuits.
24 . The electronic system package of claim 19 , wherein the die comprises one or more processor circuits.
25 . The electronic system package of claim 19 , wherein the die comprises one or more logic circuits.
26 . The electronic system package of claim 19 , wherein the die comprises one or more application specific integrated circuits.
27 . The electronic system package of claim 19 , wherein the material comprises a poly epoxide formed from one epoxide.
28 . The electronic system package of claim 19 , wherein the material comprises a poly epoxide formed from two or more epoxides.
29 . The electronic system package of claim 19 , wherein the material comprises a polyacrylate.
30 . The electronic system package of claim 19 , wherein the material comprises a polyolefin.
31 . The electronic system package of claim 19 , wherein the material comprises a polyimide.
32 . The electronic system package of claim 19 , wherein the material comprises a mixture of at least two of a poly epoxide, polyacrylate, polyimide, and polyolefin.
33 . The electronic system package of claim 19 , wherein the material comprises a copolymer of at least two of a poly epoxide, a polyacrylate, polyimide, and polyolefin.
34 . The electronic system package of claim 19 , wherein the material comprises a mixture of a poly epoxide and a polyimide.
35 . The electronic system package of claim 19 , wherein the material comprises a copolymer of a poly epoxide and a polyimide.
36 . The electronic system package of claim 19 , wherein the material has a Shore A hardness of greater than about 70.
37 . The electronic system package of claim 19 , wherein the material has a Shore D hardness of greater than about 20.
38 . An electronic system package, comprising:
a circuit board; a die; and a rigid die attach material attaching the die to the substrate.
39 . The electronic system package of claim 38 , wherein the circuit board comprises a multi-metal layer circuit board.
40 . The electronic system package of claim 38 , wherein the die comprises germanium.
41 . The electronic system package of claim 38 , wherein the die comprises one or more memory circuits.
42 . The electronic system package of claim 38 , wherein the die comprises one or more processor circuits.
43 . The electronic system package of claim 38 , wherein the die comprises one or more logic circuits.
44 . The electronic system package of claim 38 , wherein the die comprises one or more application specific integrated circuits.
45 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a poly epoxide formed from one epoxide.
46 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a poly epoxide formed from two or more epoxides.
47 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a polyacrylate.
48 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a polyolefin.
49 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a polyimide.
50 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a mixture of at least two of a poly epoxide, polyacrylate, polyimide, and polyolefin.
51 . The electronic system package of claim 3 8 , wherein the rigid die attach material comprises a copolymer of at least two of a poly epoxide, a polyacrylate, polyimide, and polyolefin.
52 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a mixture of a poly epoxide and a polyimide.
53 . The electronic system package of claim 38 , wherein the rigid die attach material comprises a copolymer of a poly epoxide and a polyimide.
54 . The electronic system package of claim 38 , wherein the rigid die attach material has a Shore A hardness of greater than about 70.
55 . The electronic system package of claim 38 , wherein the rigid die attach material has a Shore D hardness of greater than about 20.
56 . An integrated circuit package, comprising:
a ceramic substrate; a die; and a material having a low coefficient of thermal expansion attaching the die to the substrate.
57 . The integrated circuit package of claim 56 , wherein the ceramic substrate comprises a single layer ceramic substrate.
58 . The integrated circuit package of claim 56 , wherein the die comprises a processor fabricated on a semiconductor.
59 . The integrated circuit package of claim 56 , wherein the die comprises one or more memory circuits.
60 . The integrated circuit package of claim 56 , wherein the die comprises one or more logic circuits.
61 . The integrated circuit package of claim 56 , wherein the die comprises one or more application specific integrated circuits.
62 . The integrated circuit package of claim 56 , wherein the material comprises one or more polyolefins.
63 . The integrated circuit package of claim 56 , wherein the material has a Shore A hardness of greater than about 70.
64 . The integrated circuit package of claim 56 , wherein the material has a Shore D hardness of greater than about 20.
65 . The integrated circuit package of claim 56 , wherein the die includes a memory circuit.
66 . The integrated circuit package of claim 65 , wherein the memory circuit comprises one or more memory cells.
67 . The integrated circuit package of claim 65 , wherein the die includes a communication system package.
68 . A method of packaging a die, the method comprising:
positioning a die on a substrate; providing a die attach material having a Young's modulus of between about 0.1 megapascal and 20 megapascals, at a solder reflow temperature, to secure the die to the substrate; and reflowing one or more solder balls in contact with the substrate and a board.
69 . A method of packaging a die, the method comprising:
positioning a die on a substrate; and providing a die attach material having a coefficient of thermal expansion of less than about 400 (four-hundred) to secure the die to the substrate.
70 . An apparatus comprising:
a die; a first substrate having a top surface that is attached to a bottom surface of the die with a die attach material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals; a second substrate having a top surface that is attached to the bottom surface of the die with the die attach material; and a board having a top surface that is attached to a bottom surface of the first substrate with a first set of one or more solder balls and wherein the top surface of the board is attached to a bottom surface of the second substrate with a second set of one or more solder balls.
71 . The apparatus of claim 70 , further comprising a molding compound to cover at least part of the first substrate, the second substrate, the die attach material and the die.
72 . The apparatus of claim 70 , wherein the die comprises one or more memory circuits.
73 . The apparatus of claim 70 , wherein the die comprises one or more processor circuits.
74 . The apparatus of claim 70 , wherein the die attach material has a Young's modulus of between about 1 megapascals and about 4 megapascals.
75 . An apparatus comprising:
a die; a substrate having a top surface that is attached to a bottom surface of the die with a die attach material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals, wherein the top surface of the substrate is electrically coupled to the top surface of the die using one or more bonding wires; and a board having a top surface that is attached to a bottom surface of the substrate with one or more solder balls.
76 . The apparatus of claim 75 , further comprising a molding compound to cover at least part of the substrate, the die attach material and the die.
77 . The apparatus of claim 75 , wherein the die comprises one or more memory circuits.
78 . The apparatus of claim 75 , wherein the die comprises one or more processor circuits.
79 . The apparatus of claim 75 , wherein the die attach material has a Young's modulus of between about b 1 megapascals and about 4 megapascals.Join the waitlist — get patent alerts
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