Non-volatile memory and fabrication method thereof

Abstract

A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the stacked gate layer has an opening therein through these layers. The isolation layer is located on the surface of the opening. The conductive layer is disposed in the opening to cover the isolation layer.

1 - 14 . (canceled)  
   
   
       15 . A non-volatile memory comprising: 
 a gate stacked structure, disposed on a substrate, wherein the gate stacked structure comprises, sequentially from the substrate, a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer, and the gate stacked structure comprises an opening therein through the tunneling layer, the charge trapping layer, the barrier layer and the control gate layer; and    an insulation layer, disposed on a surface of the opening; and    a conductive layer, disposed in the opening, covering the insulation layer.    
   
   
       16 . The memory of  claim 15 , wherein the charge trapping layer is a polysilicon layer or a silicon nitride layer.  
   
   
       17 . The memory of  claim 15 , wherein the tunneling layer comprises silicon oxide.  
   
   
       18 . The memory of  claim 15 , wherein the barrier layer comprises silicon oxide.  
   
   
       19 . The memory of  claim 15 , wherein the control gate layer or the conductive layer comprises polysilicon.  
   
   
       20 . The memory of  claim 15  further comprising a source region and a drain region, disposed, respectively, in the substrate beside the gate stacked layer.