Method and apparatus for flip-chip packaging providing testing capability

Abstract

A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip chip semiconductor device assembly.

1 . A method of assembling a semiconductor assembly, the method comprising: 
 providing at least one semiconductor die having an active surface and a back surface, the active surface having a plurality of conductive bumps projecting therefrom;    providing an interposer substrate having a first surface and a second surface and comprising a dielectric member having at least one conductive layer thereon including a plurality of conductive traces, the interposer substrate having a plurality of recesses formed in at least one of the first and second surfaces and exposing at a bottom thereof at least a portion of one of the conductive traces, the recesses arranged in at least a first recess pattern and a second, different recess pattern; and    disposing the plurality of conductive bumps of the at least one semiconductor die in at least one of the at least the first recess pattern and the second recess pattern so that the active surface of the at least one semiconductor die lies adjacent at least one of the first surface and the second surface of the interposer substrate.    
   
   
       2 . The method of  claim 1 , wherein providing the interposer substrate comprises providing the interposer substrate with the first surface including both the at least the first recess pattern and the second recess pattern.  
   
   
       3 . The method of  claim 2 , wherein disposing further comprises matching a configuration of conductive bumps of the at least one semiconductor die to one of the at least the first recess pattern and the second recess pattern.  
   
   
       4 . The method of  claim 3 , wherein disposing comprises mounting the at least one semiconductor die over one of the at least the first recess pattern and the second recess pattern on a first die attach site commonly shared by the at least the first recess pattern and the second recess pattern.  
   
   
       5 . The method of  claim 2 , wherein providing the interposer substrate comprises providing the interposer substrate with the second surface thereof including at least a third recess pattern and a fourth recess pattern.  
   
   
       6 . The method of  claim 5 , wherein disposing comprises matching a configuration of conductive bumps of the at least one semiconductor die to at least one of the at least the third recess pattern and the fourth recess pattern.  
   
   
       7 . The method of  claim 6 , wherein disposing comprises mounting the at least one semiconductor die over the at least one of the at least third pattern and the fourth recess pattern on a second die attach site commonly shared by the at least third recess pattern and the fourth recess pattern.  
   
   
       8 . The method of  claim 2 , wherein providing the interposer substrate comprises providing the interposer substrate with the first surface thereof including at least a third recess pattern and a fourth recess pattern.  
   
   
       9 . The method of  claim 8 , wherein disposing comprises matching a configuration of conductive bumps of the at least one semiconductor die to at least one of the at least first recess pattern, the second recess pattern, the at least third recess pattern and the fourth recess pattern.  
   
   
       10 . The method of  claim 9 , wherein disposing comprises mounting the at least one semiconductor die over the at least one of the at least the first recess pattern, the second recess pattern, the at least the third recess pattern and the fourth recess pattern on a first die attach site commonly shared by each of the at least the first recess pattern, the second recess pattern, the third at least the recess pattern and the fourth recess pattern.  
   
   
       11 . The method of  claim 1 , wherein disposing comprises attaching the active surface of the at least one semiconductor die to an adhesive element on a die attach site on at least one of the first surface and the second surface of the interposer substrate.  
   
   
       12 . The method of  claim 1 , further comprising electrically testing at least interconnections between the at least one semiconductor die and the conductive traces of the interposer substrate by positioning a testing member on test pads conductively connected to the conductive traces and exposed on at least one of the first surface and the second surface proximate a periphery of the interposer substrate.  
   
   
       13 . The method of  claim 1 , further comprising dispensing encapsulation material proximate the conductive bumps in a space defined between the active surface of the at least one semiconductor die and the at least one of the first surface and the second surface of the interposer substrate.  
   
   
       14 . The method of  claim 1 , further comprising at least partially encapsulating the at least one semiconductor die and the interposer substrate with encapsulation material.  
   
   
       15 . The method of  claim 1 , further comprising mounting the second surface of the interposer substrate to another substrate with conductive elements disposed therebetween.  
   
   
       16 . A method of fabricating a substrate for mounting at least one semiconductor die in a flip chip arrangement thereto, the method comprising: 
 providing an interposer substrate having a first surface and a second surface and a dielectric member having at least one conductive layer thereon including a plurality of conductive traces;    forming a plurality of recesses in at least one of the first surface and the second surface of the interposer substrate arranged in a first recess pattern and a second, different recess pattern to expose at least portions of the conductive traces at recess bottoms and to a depth into the interposer substrate sufficient to substantially receive therein conductive bumps on an active surface of the at least one semiconductor die.    
   
   
       17 . The method of  claim 16 , wherein forming comprises sizing the recesses so that the conductive bumps on the at least one semiconductor die are receivable therein such that an active surface of the at least one semiconductor die lies adjacent the at least one of the first surface and the second surface of the interposer substrate.  
   
   
       18 . The method of  claim 16 , wherein forming comprises forming the first recess pattern and the second recess pattern in the first surface of the interposer substrate so that each of the first recess pattern and the second recess pattern share a common first die attach site for mounting the at least one semiconductor die thereto.  
   
   
       19 . The method of  claim 18 , wherein forming comprises forming the recesses of the first and second recess patterns so that each recess of the first recess pattern exposes at least a portion of a conductive trace exposed by a recess of the second recess pattern and placing each recess of the first recess pattern relatively outwardly with respect to the recess of the second recess pattern exposing at least a portion of the same conductive trace.  
   
   
       20 . The method of  claim 18 , wherein forming further comprises forming a third recess pattern and a fourth recess pattern in the second surface of the interposer substrate so that each of the third recess pattern and the fourth recess pattern share a common second die attach site for mounting the at least one semiconductor die thereto.  
   
   
       21 . The method of  claim 20 , wherein forming comprises forming recesses of the third and fourth recess patterns so that each recess of the third recess pattern exposes at least a portion of a conductive trace exposed by a recess of the fourth recess pattern and placing each recess of the third recess pattern relatively outwardly with respect to the recess of the fourth recess pattern exposing at least a portion of the same conductive trace.  
   
   
       22 . The method of  claim 20 , wherein forming comprises staggering the recesses of the third recess pattern and the fourth recess pattern with respect to the recesses of the first recess pattern and the second recess pattern.  
   
   
       23 . The method of  claim 18 , wherein forming further comprises forming at least a third recess pattern in the first surface of the interposer substrate so that each of the first recess pattern, the second recess pattern and the at least the third recess pattern share the common first die attach site for mounting the at least one semiconductor die thereto.  
   
   
       24 . The method of  claim 18 , wherein forming further comprises forming a third recess pattern and a fourth recess pattern in the first surface of the interposer substrate so that each of the first recess pattern, the second recess pattern, the third recess pattern and the fourth recess pattern share the common first die attach site for mounting the at least one semiconductor die thereto.  
   
   
       25 . The method of  claim 16 , further comprising forming an adhesive element on a die attach site on the at least one of the first surface and the second surface of the interposer substrate.  
   
   
       26 . The method of  claim 16 , further comprising forming test pads proximate a periphery of the interposer substrate and exposed on the at least one of the first surface and the second surface of the interposer substrate so that each test pad is in communication with one of the conductive traces.