Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.

1 . A semiconductor memory device comprising: 
 a semiconductor substrate;    a tunnel insulating film formed on the semiconductor substrate;    a floating gate electrode formed on the tunnel insulating film, and having a first side-surface portion positioned in an upper portion and a second side-surface portion positioned below the first side-surface portion;    an element isolation trench formed in the semiconductor substrate to be adjacent to the floating gate electrode;    a first element isolation insulating film formed along a side surface and bottom surface of the element isolation trench from the second side-surface portion of the floating gate electrode;    a second element isolation insulating film formed on the first element isolation insulating film to expose a side-surface portion in an upper portion of the first element isolation insulating film;    a first radical nitride film formed on the floating gate electrode and first and second element isolation insulating films;    an interelectrode insulating film formed on the first radical nitride film;    a nitrogen-containing film formed on the interelectrode insulating film; and    a control gate electrode formed on the nitrogen-containing film,    wherein in the second side-surface portion of the floating gate electrode, a portion of the first element isolation insulating film exists between the floating gate electrode and first radical nitride film.    
   
   
       2 . The device according to  claim 1 , wherein in the first side-surface portion of the floating gate electrode, the first element isolation insulating film does not exist between the floating gate electrode and first radical nitride film.  
   
   
       3 . The device according to  claim 1 , wherein a film thickness of the first radical nitride film in the second side-surface portion of the floating gate electrode is smaller than a film thickness of the first radical nitride film in the first side-surface portion of the floating gate electrode.  
   
   
       4 . The device according to  claim 1 , wherein the first element isolation insulating film is an oxide film.  
   
   
       5 . The device according to  claim 1 , wherein the nitrogen-containing film is a second radical nitride film.  
   
   
       6 . The device according to  claim 1 , wherein the interelectrode insulating film is one of a silicon oxide film, a metal silicate film, a multilayered film having a silicon oxide film as an upper layer, and a multilayered film having a metal silicate film as an upper layer.  
   
   
       7 . A semiconductor memory device manufacturing method comprising: 
 forming a floating gate electrode above a semiconductor substrate;    forming an interelectrode insulating film above the floating gate electrode;    forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding; and    forming a control gate electrode on the first radical nitride film.    
   
   
       8 . The method according to  claim 7 , wherein in the formation of the first radical nitride film, a nitrogen radical is formed by a gas mixture of nitrogen gas and a rare gas, or a nitrogen radical is formed by nitrogen gas alone.  
   
   
       9 . The method according to  claim 7 , wherein the interelectrode insulating film is one of a silicon oxide film, a metal silicate film, a multilayered film having a silicon oxide film as an upper layer, and a multilayered film having a metal silicate film as an upper layer.  
   
   
       10 . The method according to  claim 7 , wherein a nitriding pressure in the first radical nitriding is not less than 5 Pa and not more than 1 kPa.  
   
   
       11 . The method according to  claim 7 , wherein a nitriding pressure in the first radical nitriding is not less than 10 Pa and not more than 100 Pa.  
   
   
       12 . The method according to  claim 7 , wherein a nitriding pressure in the first radical nitriding is less than 5 Pa.  
   
   
       13 . The method according to  claim 7 , further comprising forming a second radical nitride film between the floating gate electrode and interelectrode insulating film by second radical nitriding.  
   
   
       14 . The method according to  claim 13 , wherein a nitriding pressure in the second radical nitriding is not less than 5 Pa and not more than 1 kPa.  
   
   
       15 . The method according to  claim 13 , wherein a nitriding pressure in the second radical nitriding is not less than 10 Pa and not more than 100 Pa.  
   
   
       16 . The method according to  claim 7 , further comprising: 
 forming a tunnel insulating film on the semiconductor substrate;    forming the floating gate electrode on the tunnel insulating film;    forming an element isolation trench by etching the floating gate electrode, tunnel insulating film, and semiconductor substrate;    forming a first element isolation insulating film on an exposed surface in the element isolation trench;    forming a second element isolation insulating film on the first element isolation insulating film;    selectively removing the first and second element isolation insulating films to expose a first side-surface portion in an upper portion of the floating gate electrode and a side-surface portion in an upper portion of the first element isolation insulating film;    forming a second radical nitride film on surfaces of the floating gate electrode and first and second element isolation insulating films by second radical nitriding; and    forming the interelectrode insulating film on the second radical nitride film.    
   
   
       17 . The method according to  claim 16 , wherein 
 in a second side-surface portion in a lower portion of the floating gate electrode, the first element isolation insulating film exists between the floating gate electrode and second radical nitride film, and    in the first side-surface portion of the floating gate electrode, the first element isolation insulating film does not exist between the floating gate electrode and second radical nitride film.    
   
   
       18 . The method according to  claim 16 , wherein a film thickness of the second radical nitride film in a second side-surface portion in a lower portion of the floating gate electrode is smaller than a film thickness of the second radical nitride film in the first side-surface portion of the floating gate electrode.  
   
   
       19 . The method according to  claim 16 , wherein the first element isolation insulating film is an oxide film.  
   
   
       20 . The method according to  claim 16 , wherein a second etching rate of the second element isolation insulating film is higher than a first etching rate of the first element isolation insulating film.