Shielding noisy conductors in integrated passive devices

Abstract

The specification describes a thin film Integrated Passive Device (IPD) design that achieves isolation between conductive runners by shielding the top and bottom regions of a noisy runner with metal shielding plates. The shielding plates are derived from metal interconnect layers. The invention can be implemented by merely modifying the mask pattern for the metal interconnect layers. No added elements or steps are needed to fabricate the IPDs. The invention is suitable for use in Multi-Chip Modules (MCMs) or other arrangements where digital circuits and RF circuits are in close proximity.

1 . An integrated passive device comprising a multi-level structure of at least three levels, level one, level two and level three, where the multi-level structure is situated in an essentially horizontal plane and: 
 (a) level one comprises active metallization portions and at least one level one shield metallization portion,    (b) level two comprises a noisy runner,    (c) level three comprises active metallization portions and at least one level three shield metallization portion,    wherein the level one shield metallization portion, the noisy runner, and the level three shield metallization portion are in vertical alignment.    
   
   
       2 . The device of  claim 1  including additional metallization levels.  
   
   
       3 . The device of  claim 1  wherein the level one shield metallization portion and the level three shield metallization portion are connected together with a plurality of vias extending vertically from level one to level three.  
   
   
       4 . The device of  claim 1  wherein the noisy runner is connected to a digital component.  
   
   
       5 . The device of  claim 1  wherein the noisy runner has a width W R  in the range 5-75 microns.  
   
   
       6 . The device of  claim 1  wherein the noisy runner has a width W R , the shield metallization portions have width W S , and W S >1.5 W R .  
   
   
       7 . The device of  claim 3  wherein either or both of the shield metallization portions are connected to ground.  
   
   
       8 . A method for the manufacture of an IPD comprising: 
 (a) forming a first level of metallization by selectively depositing a first metal layer pattern on an insulating substrate, the first metal pattern comprising: 
 (i) a conductive runner that interconnects with an IPD component,  
 (ii) a conductive island, the conductive island comprising a first shielding element,  
   (b) forming a first interlevel dielectric layer on the first level of metallization;    (c) forming a second level of metallization by selectively depositing a second metal layer pattern on the first interlevel dielectric layer, the second metal pattern comprising a conductive runner, the conductive runner overlying the first shielding element;    (d) forming a second interlevel dielectric layer on the second level of metallization;    (e) forming a third level of metallization by selectively depositing a third metal layer pattern on the second interlevel dielectric layer, the third metal pattern comprising: 
 (i) a conductive runner that interconnects with an IPD component,  
 (ii) a conductive island, the conductive island comprising a second shielding element, and overlying the conductive runner recited in (c).  
   
   
   
       9 . The method of  claim 8  further comprising the step of forming vias in the first and second interlevel dielectric layers.  
   
   
       10 . The method of  claim 9  further including depositing metal in the vias.  
   
   
       11 . The method of  claim 10  wherein the step of forming a third level of metallization includes connecting the first shielding element to the second shielding element.