Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs

Abstract

A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.

1 . A method for fabricating a structure on a surface of a semiconductor layer comprising: 
 providing an oxide layer on the surface of the semiconductor layer;    providing a gate structure on a first portion of said oxide layer, said gate structure having a first corner, wherein a fraction of said first portion of said oxide layer beneath said first corner defines an overlap region;    providing a photoresist layer on both said gate structure and said oxide layer, said photoresist layer leaving exposed said first corner of said gate structure and a second portion of said oxide layer adjacent said first corner and outside said gate structure; and    implanting said photoresist layer, said first corner of said gate structure, and said second portion of said oxide layer with a dosage of ions at a tilt angle non-orthogonal to the surface of the semiconductor layer to selectively dope said overlap region, said dosage being sufficient to lower a dielectric constant of said oxide layer in said overlap region and an effective surface electrical field in said overlap region.    
   
   
       2 . A method according to  claim 1 , wherein said ions are fluorine, and implant energy and said dosage are tailored to provide an ion implant concentration of about 1×10 18  atoms per cubic centimeter of fluorine.  
   
   
       3 . A method according to  claim 1 , wherein the tilt angle is about 5 to about 15 degrees from an axis orthogonal to the plane of the semiconductor layer.  
   
   
       4 . A method according to  claim 1 , wherein at least one of said ions is selected from the group consisting of fluorine and chlorine.  
   
   
       5 . A method according to  claim 1 , wherein at least one of said ions is fluorine and said implanting is carried out at an ion implantation dose of from about 1×10 13  to about 1×10 14  atoms per square centimeter, and an ion implantation energy of from about 10 KeV to about 20 KeV.  
   
   
       6 . A method according to  claim 1 , further including annealing said semiconductor layer at a temperature of about 800 to about 900 degrees centigrade for a time period of about 10 to about 15 minutes.  
   
   
       7 . A method according to  claim 1 , wherein said oxide layer thickness is about 20 to about 80 angstroms.  
   
   
       8 . A method according to  claim 1 , further comprising forming electrode spacers on both sides of said gate structure.  
   
   
       9 . A method according to  claim 1 , wherein said gate structure is comprised of polysilicon.  
   
   
       10 . A method according to  claim 1 , wherein said gate structure is a gate stack.  
   
   
       11 . A method according to  claim 1 , wherein said gate structure is a gate stack comprised of a layer of polysilicon, and additional layers selected from the group consisting of metals, metal alloys, highly doped polysilicon, silicides, and polycides (polysilicon/metal silicide stacks).  
   
   
       12 . A method according to  claim 1 , wherein said gate structure is a gate electrode comprised of a layer of polysilicon, a layer of titanium nitride deposited on top of said polysilicon layer, and a layer of tungsten deposited on top of said titanium layer.  
   
   
       13 . A method according to  claim 1 , wherein said oxide layer is formed by low pressure chemical vapor deposition to a thickness of about 20 to about 80 Angstroms.  
   
   
       14 . A method according to  claim 1 , further comprising forming lightly doped drain source/drain regions within the semiconductor layer adjoining said gate structure.  
   
   
       15 . A method according to  claim 1 , further comprising forming lightly doped drain source/drain regions within the semiconductor layer adjoining said gate structure, wherein the lightly doped regions are n-type regions formed by implanting ions, selected from the group consisting of phosphorus and arsenic, with a dosage of between about 2×10 15  to about 5×10 15  atoms per centimeter squared at an energy of between about 5 to about 15 KeV.  
   
   
       16 . A method according to  claim 1 , further comprising forming lightly doped drain source/drain regions within the semiconductor layer adjoining said gate structure, wherein the lightly doped regions are p-type regions formed by implanting boron di-fluoride ions with a dosage of between about 2×10 15  to about 5×10 15  atoms per centimeter squared at an energy of between about 10 to about 25 KeV.  
   
   
       17 . A method according to  claim 1 , further comprising forming heavily doped drain source/drain regions within the semiconductor layer adjoining the gate structure.  
   
   
       18 . A method according to  claim 1 , further comprising forming heavily doped drain source/drain regions within the semiconductor layer adjoining the gate structure, wherein the heavily doped regions are n-type regions formed by implanting ions, selected from the group consisting of phosphorus and arsenic, with a dosage of about 2×10 15  to about 5×10 15  atoms per centimeter squared at an energy of between about 5 to about 15 KeV.  
   
   
       19 . A method according to  claim 1 , further comprising forming heavily doped drain source/drain regions within the semiconductor layer adjoining the gate structure, wherein the heavily doped regions are p-type regions formed by implanting boron di-fluoride ions with a dosage of between about 2×10 15  to about 5×10 15  atoms per centimeter squared at an energy of between about 10 to about 25 KeV.  
   
   
       20 . A method according to  claim 1 , further comprising forming electrode spacers on both sides of said gate structure, said electrode spacers have widths of about 300 to about 700 Angstroms.  
   
   
       21 . A method according to  claim 1 , wherein said implanting is performed before said forming said polysilicon layer.  
   
   
       22 . A method according to  claim 1 , wherein said implanting is performed before said patterning said polysilicon layer.  
   
   
       23 . A method of reducing Gate Induced Drain Leakage (GIDL) current within Field Effect Transistors (FETs) comprising: 
 forming on a semiconductor layer a field effect transistor structure comprising a gate oxide layer, a gate electrode on a first portion of said oxide layer, said gate electrode having a first corner, wherein a fraction of said first portion of said oxide layer beneath said first corner defines an overlap region;    annealing said semiconductor layer;    providing a photoresist layer on both said gate electrode and said oxide layer, said photoresist layer leaving exposed said first corner of said gate electrode and a second portion of said oxide layer adjacent said first corner and outside said gate electrode; and    implanting said photoresist layer, said first corner of said gate electrode, and said second portion of said oxide layer with a dosage of ions at a tilt angle non-orthogonal to the surface of the semiconductor layer to selectively dope said overlap region, said dosage being sufficient to lower a dielectric constant of said oxide layer in said overlap region and lower an effective surface electrical field in said overlap region.    
   
   
       24 . A method for fabricating a structure on a semiconductor layer comprising: 
 providing an oxide layer on a semiconductor layer;    providing a polysilicon layer on said oxide layer;    patterning said polysilicon layer into a gate structure on a first portion of said oxide layer, said gate structure having a first corner on said oxide layer, wherein a fraction of said first portion of said oxide layer beneath said first corner defines an overlap region;    annealing said semiconductor layer;    providing a photoresist layer on both said gate structure and said oxide layer, said photoresist layer leaving exposed a side of said first corner of said gate structure and a second portion of said oxide layer adjacent said first corner and outside said gate electrode; and    implanting said photoresist layer, said first corner of said gate electrode, and said second portion of said oxide layer with a dosage of ions at a tilt angle non-orthogonal to the surface of the semiconductor layer to selectively dope said overlap region, said dosage being sufficient to increase the electrical gate oxide thickness only in said overlap region.    
   
   
       25 . A method for fabricating a structure on a semiconductor layer comprising: 
 providing an oxide layer on a semiconductor layer;    providing a polysilicon layer on said oxide layer;    patterning said polysilicon layer into a gate structure on a first portion of said oxide layer, said gate structure having a first corner on said oxide layer, wherein a fraction of said first portion of said oxide layer beneath said first corner defines an overlap region;    providing drain source/drain regions within the semiconductor layer adjoining said gate structure;    annealing said semiconductor layer;    implanting said photoresist layer, said first corner of said gate structure, and said second portion of said oxide layer with a dosage of ions at a tilt angle non-orthogonal to the surface of the semiconductor layer to selectively dope said overlap region, said dosage being sufficient to lower a dielectric constant of said oxide layer in said overlap region and lower an effective surface electrical field in said overlap region.    
   
   
       26 . A method for fabricating a structure on a semiconductor layer comprising: 
 providing an oxide layer on a semiconductor layer;    providing a polysilicon layer on said oxide layer;    patterning said polysilicon layer into a gate structure having first and second leading edges, and to expose at least portions of said oxide layer adjacent said first and second leading edges;    providing a resist layer which exposes a portion of said gate structure and at least a portion of said oxide layer adjacent said first leading edge outside said gate structure; and    implanting ions, at an angle nonorthogonal to said oxide layer, into said exposed portions of said gate structure and said oxide layer to dope an overlap region beneath said gate structure adjacent said first leading edge and inward of said second leading edge to a predetermined ion implant concentration which is sufficient to lower a dielectric constant of the oxide layer in said overlap region and increase electrical gate oxide thickness only in said overlap region.