Methods for Transistor Formation Using Selective Gate Implantation

Abstract

Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

1 - 21 . (canceled)  
   
   
       22 . A method of fabricating a semiconductor device, comprising 
 forming a gate structure over a semiconductor substrate;    performing a first implantation to provide dopants to prospective source/drain regions in the substrate;    performing a second implantation to selectively provide dopants into the gate structure substantially without providing dopants to the prospective source/drain regions; and    performing a third implantation to provide dopants to the prospective source/drain regions.    
   
   
       23 . The method of  claim 22 , wherein performing the first implantation comprises performing one of an LDD implant process and a source/drain implant process, and wherein performing the third implantation comprises performing the other of the LDD implant process and the source/drain implant process.  
   
   
       24 . The method of  claim 22 , wherein performing the second implantation comprises: 
 forming a film over the semiconductor device after performing the first implantation;    exposing at least a portion of the gate structure through the film; and    selectively implanting dopants into the exposed portion of the gate structure.    
   
   
       25 . The method of  claim 24 , wherein forming the film comprises depositing a substantially conformal film over the semiconductor device, and wherein exposing at least a portion of the gate structure comprises planarizing the semiconductor device to expose a portion of the gate structure using a chemical mechanical polishing process.  
   
   
       26 . The method of  claim 24 , wherein forming the film comprises depositing a substantially non-conformal film over the semiconductor device, and wherein exposing at least a portion of the gate structure comprises etching the semiconductor device to expose a portion of the gate structure using a reactive ion etch process.