US2006270162A1PendingUtilityA1

High voltage metal-oxide-semiconductor transistor devices and method of making the same

Assignee: LIN CHIEN-MINGPriority: May 26, 2005Filed: Jan 23, 2006Published: Nov 30, 2006
Est. expiryMay 26, 2025(expired)· nominal 20-yr term from priority
H10D 84/0147H10D 84/0144H10D 84/038H10B 41/49H10B 41/40
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Claims

Abstract

A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.

Claims

exact text as granted — not AI-modified
1 . A metal-oxide-semiconductor device, comprising: 
 a semiconductor substrate;    a gate dielectric layer with a thickness t1 formed on the semiconductor substrate;    a gate electrode formed on the gate dielectric layer;    a salicide block lug portions with a thickness t 2  being contiguous with the gate dielectric layer, wherein the salicide block lug portions are disposed on two opposite sides of the gate electrode with an offset distance “d” from sidewalls of the gate electrode, wherein t 2 <t 1 ;    a source/drain region disposed adjacent to the salicide block lug portions; and    a salicide layer formed on the source/drain region that is kept the offset distance “d” away from the gate electrode.    
   
   
       2 . The metal-oxide-semiconductor device according to  claim 1  wherein the thickness t 1 >400 angstroms.  
   
   
       3 . The metal-oxide-semiconductor device according to  claim 1  wherein the thickness t 2 >100 angstroms.  
   
   
       4 . The metal-oxide-semiconductor device according to  claim 1  wherein the offset distance “d” is in a range of 20˜500 angstroms.  
   
   
       5 . The metal-oxide-semiconductor device according to  claim 1  wherein the metal-oxide-semiconductor device is a high-voltage (18V or higher voltage) metal-oxide-semiconductor transistor device.

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