Methods of forming semiconductor devices and electrical interconnect structures in semiconductor devices and intermediate structures formed thereby

Abstract

Methods of forming semiconductor device assemblies include forming a depression in a semiconductor chip while the semiconductor chip is disposed in the stack, and filling the depression with conductive material. Additional methods include ablating material of a semiconductor device to form a depression, and subsequently filling the depression conductive material. In some embodiments, the depression may be formed in a sidewall of the semiconductor device, and the conductive material may be exposed at the sidewall of the semiconductor device. Yet additional methods include causing a laser machining apparatus to execute a computer program that causes the laser machining apparatus to substantially automatically ablate a plurality of depressions in a surface of a wafer in a predetermined pattern. Intermediate structures formed during fabrication of a semiconductor device include laser ablation slag disposed in at least one depression in a layer of material extending over at least a portion of a wafer.

1 . A method of forming a semiconductor device assembly including a plurality of semiconductor chips, the method comprising: 
 assembling a plurality of semiconductor chips into a stack of semiconductor chips;    forming at least one depression in at least one semiconductor chip in the stack of semiconductor chips while the at least one semiconductor chip is disposed in the stack of semiconductor chips; and    filling the at least one depression with a conductive material.    
   
   
       2 . The method of  claim 1 , wherein forming at least one depression in at least one semiconductor chip in the stack of semiconductor chips comprises forming at least one depression through more than one semiconductor chip in the stack of semiconductor chips.  
   
   
       3 . The method of  claim 1 , wherein forming at least one depression in a semiconductor chip in the stack of semiconductor chips comprises ablating at least partially through the at least one semiconductor chip in the stack of semiconductor chips using a laser.  
   
   
       4 . The method of  claim 3 , further comprising etching the at least one semiconductor chip in the stack of semiconductor chips after ablating at least partially through the at least one semiconductor chip in the stack of semiconductor chips using a laser.  
   
   
       5 . A method of substantially simultaneously forming a plurality of semiconductor devices, the method comprising: 
 providing a laser machining apparatus including a platen;    positioning a wafer comprising a plurality of at least partially formed individual semiconductor devices on the platen of the laser machining apparatus;    providing a computer program associated with the laser machining apparatus; and    causing the laser machining apparatus to execute the computer program, the computer program causing the laser machining apparatus to emit a laser beam towards a surface of the wafer and traverse the surface of the wafer in a selected pattern to substantially automatically ablate a plurality of depressions in the surface of the wafer in a predetermined pattern.    
   
   
       6 . The method of  claim 5 , further comprising filling the plurality of depressions in the surface of the wafer with conductive material to form a plurality of electrical pathways.  
   
   
       7 . The method of  claim 6 , further comprising etching the plurality of depressions in the surface of the wafer subsequent to ablating the plurality of depressions and prior to filling the plurality of depressions in the surface of the wafer with conductive material.  
   
   
       8 . The method of  claim 5 , wherein causing the laser machining apparatus to execute the computer program comprises ablating a first plurality of depressions extending a first depth into the layer of material and a second plurality of depressions extending a second depth into the layer of material, the second depth being greater than the first depth.  
   
   
       9 . The method of  claim 5 , wherein ablating a first plurality of depressions and a second plurality of depressions comprises ablating a plurality of channels extending generally laterally across a surface of the wafer, and wherein the second plurality of depressions comprises a plurality of vias extending generally vertically into the surface of the wafer.  
   
   
       10 . A method of forming an electrical interconnect structure for a semiconductor device, the method comprising: 
 providing a semiconductor device including at least one semiconductor chip, the semiconductor device having a top surface, a bottom surface, and at least one sidewall;    ablating a layer of material of the semiconductor device using a laser device to form at least one elongated depression extending laterally in the layer of material to the at least one sidewall of the semiconductor device;    filling the at least one elongated depression with electrically conductive material; and    exposing the conductive material at the at least one sidewall.    
   
   
       11 . The method of  claim 10 , further comprising etching the at least one elongated depression subsequent to ablating the layer of material and prior to filling the at least one elongated depression with electrically conductive material.  
   
   
       12 . The method of  claim 10 , further comprising planarizing the electrically conductive material to electrically isolate the electrically conductive material in the at least one elongated depression.  
   
   
       13 . A method of forming an electrical interconnect structure for a semiconductor device, the method comprising: 
 providing a semiconductor device including at least one semiconductor chip, the semiconductor device having a top surface, a bottom surface, and at least one sidewall;    forming a depression in the at least one sidewall of the semiconductor device using a laser device;    filling the depression with a conductive material, the conductive material communicating electrically with at least one active component of the at least one semiconductor chip; and    exposing the conductive material at the at least one sidewall.    
   
   
       14 . The method of  claim 10 , further comprising etching the at least one elongated depression subsequent to ablating the layer of material and prior to filling the at least one elongated depression with electrically conductive material.  
   
   
       15 . An intermediate structure formed during fabrication of a semiconductor device, the intermediate structure comprising: 
 a wafer comprising a plurality of at least partially formed individual semiconductor devices;    a layer of material extending over at least a portion of the surface of the wafer, the at least a portion of the surface extending over the plurality of at least partially formed individual semiconductor device;    a plurality of depressions extending at least partially through the layer of material; and    laser ablation slag disposed in at least one depression of the plurality of depressions.    
   
   
       16 . The intermediate structure of  claim 15 , wherein the plurality of depressions comprise a first plurality of depressions extending a first depth into the layer of material and a second plurality of depressions extending a second depth into the layer of material, the second depth being greater than the first depth.  
   
   
       17 . The intermediate structure of  claim 16 , wherein the first plurality of depressions comprises a plurality of channels extending laterally in the layer of material along a surface thereof, and wherein the second plurality of depressions comprises a plurality of vias extending vertically through the layer of material.  
   
   
       18 . The intermediate structure of  claim 17 , wherein at least one via of the plurality of vias communicates with at least one channel of the plurality of channels.  
   
   
       19 . The intermediate structure of  claim 15 , wherein the wafer comprises a silicon wafer.  
   
   
       20 . The intermediate structure of  claim 15 , wherein at least one depression of the plurality of depressions extends entirely through at least one at least partially formed individual semiconductor device of the plurality of at least partially formed individual semiconductor devices.