Reducing oxidation of phase change memory electrodes

Abstract

A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.

1 . A method comprising: 
 forming a chalcogenide over a lower electrode of a phase change memory; and    reducing oxygen exposure of said chalcogenide layer to reduce oxidation of said lower electrode.    
   
   
       2 . The method of  claim 1  including forming a stack including an upper electrode, the chalcogenide, and a lower electrode.  
   
   
       3 . The method of  claim 2  including using photoresist to pattern and etch said upper electrode.  
   
   
       4 . The method of  claim 3  including refraining from using a high temperature oxygen plasma treatment to remove said photoresist.  
   
   
       5 . The method of  claim 3  including stopping the etching of said stack before reaching said chalcogenide.  
   
   
       6 . The method of  claim 4  including stopping the etching of said stack before reaching a layer which overlies the chalcogenide.  
   
   
       7 . The method of  claim 6  including removing the photoresist before removing the layer overlying said chalcogenide.  
   
   
       8 . The method of  claim 7  including forming a stack including an ovonic threshold switch, as well as said upper electrode, and etching through said upper electrode down to said ovonic threshold switch.  
   
   
       9 . The method of  claim 8  including applying an oxidation barrier layer after etching through said chalcogenide.  
   
   
       10 . The method of  claim 1  including forming a stack including an upper electrode, the chalcogenide, and covering said stack with an oxidation barrier to prevent oxygen infiltration into said chalcogenide.  
   
   
       11 . A phase change memory comprising: 
 a chalcogenide layer;    a lower electrode under said chalcogenide layer; and    an oxidation barrier over said chalcogenide layer and lower electrode.    
   
   
       12 . The memory of  claim 11  wherein said oxidation barrier is formed of a material selected from the group including silicon nitride, S i O x N y , and aluminum oxide.  
   
   
       13 . The memory of  claim 11  including an ovonic threshold switch.  
   
   
       14 . The memory of  claim 13  wherein said ovonic threshold switch is formed over said chalcogenide layer.  
   
   
       15 . The memory of  claim 11  including an oxide over said oxidation barrier.  
   
   
       16 . The memory of  claim 11  including a chalcogenide layer and at least one upper electrode having aligned side edges to form a stack, said oxidation barrier formed over said aligned side edges.  
   
   
       17 . The memory of  claim 16  including an ovonic threshold switch in said stack.  
   
   
       18 . The memory of  claim 11  including a stack of layers including said chalcogenide layer, a top electrode, a barrier film over said top electrode, and an ovonic threshold switch over said barrier film.  
   
   
       19 . The memory of  claim 18  wherein said ovonic threshold switch includes a chalcogenide material that does not change phase.  
   
   
       20 . The memory of  claim 19  including an electrode over said ovonic threshold switch.  
   
   
       21 . A system comprising: 
 a controller;    a static random access memory coupled to said controller; and    a phase change memory including a lower electrode, a chalcogenide layer over said lower electrode, and an oxidation barrier over said chalcogenide layer and said lower electrode.    
   
   
       22 . The system of  claim 21  wherein said oxidation barrier is formed of a material selected from the group including silicon nitride, S i O x N y , and aluminum oxide.  
   
   
       23 . The system of  claim 21  wherein said phase change memory includes an ovonic threshold switch.  
   
   
       24 . The system of  claim 23  wherein said ovonic threshold switch is formed over said chalcogenide layer.  
   
   
       25 . The system of  claim 21  wherein said phase change memory includes an oxide over said oxidation barrier.  
   
   
       26 . The system of  claim 21  wherein said phase change memory includes a chalcogenide layer and at least one upper electrode having aligned side edges to form a stack, said oxidation barrier formed over said aligned side edges.  
   
   
       27 . The system of  claim 26  including an ovonic threshold switch in said stack.  
   
   
       28 . The system of  claim 21  wherein said phase change memory includes a stack of layers including said chalcogenide layer, a top electrode, a barrier film over said top electrode, and an ovonic threshold switch over said barrier film.  
   
   
       29 . The system of  claim 28  wherein said ovonic threshold switch includes a chalcogenide material that does not change phase.  
   
   
       30 . The system of  claim 29  including an electrode over said ovonic threshold switch.