Collector layer structure for a double hetero-junction bipolar transistor for power amplification applications

Abstract

An indium phosphide based double hetero junction bipolar transistor with an increased collector-base breakdown voltage and a reduced operational knee voltage is provided by manipulating the conductivity in the collector region. The collector is formed using layers of different conductivities, with a region of the collector relatively close to the base being unintentionally or low doped. A voltage drop across the unintentionally doped region reduces the maximum value of the electric field and the velocity of carriers injected into the collector region at the base-collector junction. The conductivity throughout the collector region may be graded such that the highest conductivity occurs near the sub-collector and lowest conductivity occurs near the base region.

1 - 39 . (canceled)  
   
   
       40 . An indium phosphide-based semiconductor double hetero-structure bipolar transistor comprising: 
 an emitter region having a first bandgap;    a base region in electrical communication with the emitter region, the base region having a second bandgap different from the first bandgap;    a collector region containing indium and phosphorous and in electrical communication with the base and the emitter regions, the collector region having a third bandgap different from the second bandgap; and    a sub-collector in electrical communication with the collector region, wherein the collector region comprises a first layer and a second layer, the first layer is closer to the sub-collector than the second layer, a carrier concentration of the first and second layers gradually increasing from the second layer to the first layer.    
   
   
       41 . The transistor as recited in  claim 40 , wherein the carrier concentrations of the first and second layers are substantially constant throughout the first and second layers.  
   
   
       42 . The transistor as recited in  claim 41 , wherein the carrier concentration of the first layer is at least 50% greater than the carrier concentration of the second layer.  
   
   
       43 . The transistor as recited in  claim 40 , wherein the collector region further comprises at least one additional layer disposed between the first layer and the sub-collector, a carrier concentration of the additional layer greater than the carrier concentration of the first layer.  
   
   
       44 . The transistor as recited in  claim 43 , wherein a plurality of additional layers are disposed between the first layer and the sub-collector, carrier concentrations of the additional layers increasing with increasing distance from the first layer.  
   
   
       45 . The transistor as recited in  claim 44 , wherein the carrier concentrations of the additional layers are substantially constant throughout each of the additional layers.  
   
   
       46 . The transistor as recited in  claim 44 , wherein the carrier concentration of at least one of the additional layers is graded.  
   
   
       47 . The transistor as recited in  claim 40 , further comprising a transition region between the base region and the collector region, the transition region containing a plurality of transition layers each having a bandgap different from the second and third bandgaps.