Cavity ball grid array apparatus having improved inductance characteristics
Abstract
A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging. A ground plane, may extend over the adhesive layer and frame the cavity, or also extend over the cavity to provide an enclosure for the die. In the former case, an encapsulant is applied over the die and electrical connections to the traces.
Claims
exact text as granted — not AI-modified1 . A semiconductor die package, comprising:
a package substrate having a surface including circuit traces extending from a central area on the surface to a peripheral area on the surface, the central area defining a die-attach location; an adhesive layer disposed over the peripheral area on the surface of the package substrate; and a conductive element disposed over the adhesive layer, wherein the adhesive layer provides an electrical connection between the conductive element and the circuit traces.
2 . The semiconductor die package of claim 1 , further comprising an insulative layer over the circuit traces having at least one aperture permitting electrical contact between the circuit traces and the conductive element.
3 . The semiconductor die package of claim 2 , wherein the insulative layer comprises a solder mask.
4 . The semiconductor die package of claim 1 , wherein a semiconductor die is electrically connected to the package substrate with at least one wire bond.
5 . The semiconductor die package of claim 1 , wherein a semiconductor die is electrically connected to the package substrate in a flip-chip configuration by conductive elements extending from an active surface of the semiconductor die.
6 . The semiconductor die package of claim 1 , wherein the conductive element includes an aperture therethrough aligned with the central area.
7 . The semiconductor die package of claim 1 , wherein the conductive element extends over the central area.
8 . The semiconductor die package of claim 7 , further comprising an underside recess in the conductive element aligned with the central area.
9 . The semiconductor die package of claim 7 , wherein the conductive element includes a protrusion defining a recess thereunder that is aligned with the central area.
10 . The semiconductor die package of claim 1 , wherein a semiconductor die is attached to a conductive die-attach pad on the surface of the package substrate.
11 . The semiconductor die package of claim 1 , further comprising at least one conductive element on an opposing surface of the package substrate and in electrical communication with the circuit traces.
12 . A computer system, comprising:
an input device; an output device; a processor device; and a memory device; at least one of the processor device and the memory device being configured as: a package substrate having a surface including circuit traces extending from a central area on the surface to a peripheral area on the surface, the central area defining a die-attach location; an adhesive layer disposed over the peripheral area on the surface of the package substrate; and a conductive element disposed over the adhesive layer, wherein the adhesive layer provides an electrical connection between the conductive element and the circuit traces.Join the waitlist — get patent alerts
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