Semiconductor device

Abstract

A semiconductor device including: a semiconductor layer including an element formation region and an isolation region provided around the element formation region; an element formed in the element formation region; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric; a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and a bump formed in the opening and having a rectangular planar shape having a short side and a long side, the bump at least partially covering the element when viewed from a top side, and the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from the short side of the bump being a forbidden region.

1 . A semiconductor device comprising: 
 a semiconductor layer including an element formation region and an isolation region provided around the element formation region;    an element formed in the element formation region;    an interlayer dielectric formed above the semiconductor layer;    an electrode pad formed above the interlayer dielectric;    a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and    a bump formed in the opening and having a rectangular planar shape having a short side and a long side, the bump at least partially covering the element when viewed from a top side,    the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from the short side of the bump being a forbidden region.    
   
   
       2 . The semiconductor device as defined in  claim 1 , 
 wherein the forbidden region is a range within 2.0 to 3.0 micrometers outward from a line extending vertically downward from the short side of the bump.    
   
   
       3 . The semiconductor device as defined in  claim 1 , 
 wherein the forbidden region is a range within 2.0 to 3.0 micrometers inward from a line extending vertically downward from the short side of the bump.    
   
   
       4 . A semiconductor device comprising: 
 a semiconductor layer including an element formation region and an isolation region provided around the element formation region;    an element formed in the element formation region;    an interlayer dielectric formed above the semiconductor layer;    an electrode pad formed above the interlayer dielectric;    a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad;    a bump formed in the opening and at least partially covering the element when viewed from a top side; and    a lead wire formed on the bump and overlapping one side of the bump when viewed from a top side,    the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from the one side of the bump and a side opposite to the one side being a forbidden region in which the element formation region is not provided.    
   
   
       5 . The semiconductor device as defined in  claim 4 , 
 wherein the forbidden region is a range within 2.0 to 3.0 micrometers outward from a line extending vertically downward from the one side and the side opposite the one side of the bump.    
   
   
       6 . The semiconductor device as defined in  claim 4 , 
 wherein the forbidden region is a range within 2.0 to 3.0 micrometers inward from a line extending vertically downward from the one side and the side opposite the one side of the bump.    
   
   
       7 . A semiconductor device comprising: 
 a semiconductor layer including an element formation region and an isolation region provided around the element formation region;    an element formed in the element formation region;    an interlayer dielectric formed above the semiconductor layer;    an electrode pad formed above the interlayer dielectric;    a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and    a bump formed in the opening and covering the element when viewed from a top side,    the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from an edge of the bump being a forbidden region.    
   
   
       8 . The semiconductor device as defined in  claim 7 , 
 wherein the forbidden region is a range within 2.0 to 3.0 micrometers outward from a line extending vertically downward from the edge of the bump.    
   
   
       9 . The semiconductor device as defined in  claim 7 , 
 wherein the forbidden region is a range within 2.0 to 3.0 micrometers inward from a line extending vertically downward from the edge of the bump.    
   
   
       10 . The semiconductor device as defined in  claim 1 , 
 wherein the element is a transistor.    
   
   
       11 . The semiconductor device as defined in  claim 1 , 
 wherein the forbidden region is a forbidden region for a low-voltage-drive transistor.    
   
   
       12 . The semiconductor device as defined in  claim 11 , 
 wherein a high-voltage transistor is formed in the forbidden region.    
   
   
       13 . The semiconductor device as defined in  claim 4 , 
 wherein the element is a transistor.    
   
   
       14 . The semiconductor device as defined in  claim 4 , 
 wherein the forbidden region is a forbidden region for a low-voltage-drive transistor.    
   
   
       15 . The semiconductor device as defined in  claim 14 , 
 wherein a high-voltage transistor is formed in the forbidden region.    
   
   
       16 . The semiconductor device as defined in  claim 7 , 
 wherein the element is a transistor.    
   
   
       17 . The semiconductor device as defined in  claim 7 , 
 wherein the forbidden region is a forbidden region for a low-voltage-drive transistor.    
   
   
       18 . The semiconductor device as defined in  claim 17 , 
 wherein a high-voltage transistor is formed in the forbidden region.