Circuit board structure and method for fabricating the same

Abstract

A circuit board structure and a method for fabricating the same are proposed. A plurality of conductive bumps and a first solder mask are formed on a carrier board, and the first solder mask is filled in the gaps between the conductive bumps and the conductive bumps are exposed. A first circuit layer and a first heat sink are formed on the first solder mask and the conductive bumps. A second heat sink is formed on the first heat sink, and a dielectric layer is formed on the first circuit layer and the first solder mask except the first and second heat sinks. A second circuit layer is formed on the dielectric layer and is electrically conductive to the first circuit layer. A third heat sink is formed on the second heat sink and a heat sink used for a chip mounting thereon is embedded in the dielectric layer. Therefore, the dimension of the circuit board is reduced and it is conformed to the dimension minimization progress of electronic devices.

1 . A method for fabricating a circuit board structure, the method comprising: 
 forming on a carrier board a plurality of conductive bumps and first solder masks filled in gaps between the conductive bumps for exposing the conductive bumps;    forming on the first solder masks and the conductive bumps a conductive layer and on the conductive layer a first resistive layer having a plurality of openings for exposing part of the conductive layer;    forming in the openings of the first resistive layer a first circuit layer and a first heat sink;    forming on the first heat sink, the first resistive layer and the first circuit layer a second resistive layer having a plurality of openings for exposing the first heat sink;    forming a second heat sink on the first heat sink exposed to a region outside of the openings of the second resistive layer;    removing the second resistive layer, the first resistive layer and the conductive layer covered by the first resistive layer, and forming a dielectric layer on the first circuit layer and the first solder mask where neither the first heat sink nor the second heat sink is formed; and    forming on the second heat sink a third heat sink, and forming on the dielectric layer a second circuit layer electrically conductive to the first circuit layer.    
     
     
         2 . The method of  claim 1 , wherein forming the conductive bumps comprises: 
 forming on the carrier board a resistive layer having a plurality of openings; and    forming the conductive bumps in the openings.    
     
     
         3 . The method of  claim 2 , wherein the forming the conductive bumps further comprises removing the resistive layer.  
     
     
         4 . The method of  claim 1 , wherein at least one of the conductive bumps comprises one selected from solder tin and metal materials.  
     
     
         5 . The method of  claim 1 , wherein forming the second circuit layer comprises: 
 forming in the dielectric layer a plurality of vias for exposing the first circuit layer;    forming a conductive layer on the dielectric layer, the second heat sink and the vias;    forming on the conductive layer a third resistive layer having a plurality of openings; and    electroplating and forming in the openings of the third resistive layer the second circuit layer, the conductive vias and the third heat sink, wherein the second circuit layer is electrically conductive by the conductive vias in the dielectric layer to the first circuit layer, and the third heat sink is formed on the second heat sink.    
     
     
         6 . The method of  claim 5 , wherein forming the second circuit layer further comprises: 
 removing the third resistive layer and the conductive layer covered thereby.    
     
     
         7 . The method of  claim 1  further comprising: 
 forming on the second circuit layer a second solder mask having a varieties of openings for exposing the third heat sink and part of the second circuit layer as electrically conductive pads; and    removing the carrier board.    
     
     
         8 . The method of  claim 7 , wherein the electrically conductive pads are covered by a metal protection layer.  
     
     
         9 . The method of  claim 1  further comprising: 
 performing a circuit build-up process on the second circuit layer and the third heat sink to form on the second circuit layer a circuit build-up structure and increase a thickness of the heat sink, the circuit build-up structure having an external surface formed with a circuit layer formed with a plurality of electrically conductive pads;    forming on the circuit build-up structure and external surfaces of the heat sinks a second solder mask having a plurality of openings for exposing the electrically conductive pads and the heat sinks; and    removing the carrier board.    
     
     
         10 . The method of  claim 9 , wherein the electrically conductive pads having a surface formed with a metal protection layer.  
     
     
         11 . A circuit board structure comprising: 
 a dielectric layer having a first surface and a second surface;    a plurality of heat sinks embedded in the dielectric layer and protruding to a region above the second surface of the dielectric layer;    a first circuit layer embedded in the dielectric layer and disposed evenly with the first surface of the dielectric layer; and    a second circuit layer formed on the second surface of the dielectric layer second surface and electrically conductive to the first circuit layer, wherein the first circuit layer is electrically conductive by a conductive via formed in the dielectric layer to the second circuit layer.    
     
     
         12 . The circuit board structure of  claim 11 , wherein the heat sinks comprise a third heat sink protruding to a region above the second surface of the dielectric layer, and a first heat sink and a second heat sink, both of which are embedded in the dielectric layer.  
     
     
         13 . The circuit board structure of  claim 11  further comprising: 
 a first solder mask covered on the first circuit layer and the first surface of the dielectric layer and having a pluralities of openings for exposing part of the first circuit layer; and    a plurality of conductive bumps formed in the openings of the first solder mask.    
     
     
         14 . The circuit board structure of  claim 13 , wherein at least one of the conductive bumps comprises one selected from the group consisting of solder tin and a metal material.  
     
     
         15 . The circuit board structure of  claim 11  further comprising on the second circuit layer, the third heat sink and the second surface of the dielectric layer a second solder mask having a plurality of openings for exposing the third heat sink and part of second circuit layer as a plurality of electrically conductive pads.  
     
     
         16 . The circuit board structure of  claim 15  further comprising a metal protection layer formed on the electrically conductive pads.  
     
     
         17 . The circuit board structure of  claim 11  further comprising a circuit build-up structure formed on the second circuit layer and the second surface of the dielectric layer second surface, and a heat sink formed on the third heat sink.  
     
     
         18 . The circuit board structure of  claim 17  further comprising a solder mask formed on the circuit build-up structure and having a plurality of openings for exposing the electrically conductive pads on a circuit layer on an external surface of the circuit build-up structure.  
     
     
         19 . The circuit board structure of  claim 18  further comprising a metal protection layer formed on the electrically conductive pads.