Vertical-channel junction field-effect transistors having buried gates and methods of making

Abstract

Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.

1 . A semiconductor device comprising: 
 a substrate layer comprising a semiconductor material of a first conductivity type;    a drift layer on the substrate layer, the drift layer comprising a semiconductor material of the first conductivity type;    a gate region on the drift layer, wherein the gate region comprises a semiconductor material of a second conductivity type different than the first conductivity type;    a channel layer of the first conductivity type on the drift layer and covering a first portion of the gate region; and    a source layer of the first conductivity type on the channel layer.    
     
     
         2 . The device of  claim 1 , wherein the drift layer is on a buffer layer comprising a semiconductor material of the first conductivity type and wherein the buffer layer is on the semiconductor substrate.  
     
     
         3 . The device of  claim 2 , wherein the buffer layer has a dopant concentration greater than 1×10 18 /cm 3 .  
     
     
         4 . The device of  claim 1 , wherein the semiconductor material of the substrate layer, the drift layer, the gate regions and the channel layer is silicon carbide.  
     
     
         5 . The device of  claim 1 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material.  
     
     
         6 . The device of  claim 1 , wherein the drift layer has a thickness greater than 5 μm.  
     
     
         7 . The device of  claim 1 , wherein the gate region has a thickness greater than 0.5 μm.  
     
     
         8 . The device of  claim 1 , wherein the gate region has a dopant concentration greater than 1×10  19 /cm 3 .  
     
     
         9 . The device of  claim 1 , wherein the substrate layer has a dopant concentration greater than 1×10 18 /cm 3 .  
     
     
         10 . The device of  claim 1 , wherein the drift layer has a dopant concentration of 5×10 14 /cm 3  to 1×10 17 /cm 3 .  
     
     
         11 . The device of  claim 1 , wherein the channel layer has a dopant concentration of 1×10 15 /cm 3  to 5×10 17 /cm 3 .  
     
     
         12 . The device of  claim 1 , further comprising an ohmic contact on the substrate opposite the drift layer, an ohmic contact on the source layer on the channel layer over the gate regions, and an ohmic contact on the gate region.  
     
     
         13 . The device of  claim 1 , wherein the first portion of the gate region comprises a plurality of elongate segments oriented parallel to one another in spaced relation with semiconductor material of the channel layer between adjacent elongate segments.  
     
     
         14 . The device of  claim 1 , further comprising metal layers on the ohmic contacts.  
     
     
         15 . The device of  claim 1 , further comprising an edge termination structure.  
     
     
         16 . The device of  claim 15 , wherein the edge termination structure comprises one or more continuous regions of a semiconductor material of the second conductivity type circumscribing the gate region.  
     
     
         17 . The device of  claim 16 , wherein regions of semiconductor material of the first conductivity type are adjacent the one or more continuous regions of semiconductor material of the second conductivity type circumscribing the gate region.  
     
     
         18 . The device of  claim 1 , wherein the device is a vertical junction field effect transistor.  
     
     
         19 . The device of  claim 1 , wherein the device is a static induction transistor.  
     
     
         20 . The device of  claim 1 , wherein the source layer has a thickness greater than 0.5 μm.  
     
     
         21 . The device of  claim 1 , wherein the source layer has a dopant concentration >1×10 19 /cm 3 .  
     
     
         22 . The device of  claim 1 , further comprising a Schottky metal layer in contact with the drift layer.  
     
     
         23 . The device of  claim 1 , wherein the source layer is epitaxially grown on the channel layer.  
     
     
         24 . The method of  claim 1 , wherein the source layer is implanted in the channel layer.  
     
     
         25 . A method of making a semiconductor device comprising: 
 selectively etching through a gate layer of semiconductor material of a second conductivity type on a drift layer of semiconductor material of a first conductivity type different than the second conductivity type to expose material of the drift layer, wherein the drift layer is on a semiconductor substrate;    depositing a channel layer of semiconductor material of the first conductivity type on exposed portions of the gate and drift layers to cover the gate layer;    depositing a source layer of semiconductor material of the first conductivity type on the channel layer or, alternatively, implanting a source layer of semiconductor material of the first conductivity type in the channel layer;    selectively etching through the channel layer in a peripheral region of the device to expose a portion of the underlying gate layer, wherein an unexposed portion of the gate layer remains covered by the channel and source layers;    depositing a layer of a dielectric material on exposed surfaces of the source layer, the channel layer and the gate layer;    selectively etching through the dielectric layer over the portion of the gate layer exposed during etching of the channel layer to expose underlying gate layer; and    selectively etching through the dielectric layer over the source layer on the unexposed portion of the gate layer to expose underlying source layer.    
     
     
         26 . The method of  claim 25 , further comprising forming contacts on exposed source layer, exposed gate layer and on a surface of the semiconductor substrate opposite the drift layer.  
     
     
         27 . The method of  claim 25 , wherein the dielectric layer over the portion of the gate layer exposed during etching of the channel layer and the dielectric layer over the source layer are etched simultaneously.  
     
     
         28 . The method of  claim 26 , wherein forming contacts comprises depositing an ohmic contact material and subsequently depositing an electrically conductive metal on the ohmic contact material.  
     
     
         29 . The method of  claim 25 , wherein the dielectric layer over the source layer is selectively etched such that dielectric material remains on the periphery of the central region.  
     
     
         30 . The method of  claim 25 , wherein selectively etching through the gate layer forms a plurality of elongate regions of the semiconductor material of the second conductivity type oriented parallel and in spaced relation to one another on the drift layer in the central region of the device.  
     
     
         31 . The method of  claim 25 , wherein selectively etching through the gate layer forms one or more continuous regions of the semiconductor material of the second conductivity type on the drift layer and circumscribing the gate region.  
     
     
         32 . The method of  claim 30 , wherein depositing a channel layer comprises depositing semiconductor material of the first conductivity type between the adjacent elongate regions of semiconductor material of the second conductivity type.  
     
     
         33 . The method of  claim 31 , wherein depositing a channel layer comprises depositing semiconductor material of the first conductivity type on the drift layer adjacent the one or more continuous regions of semiconductor material of the second conductivity type circumscribing the gate region.  
     
     
         34 . The method of  claim 25 , wherein the channel layer is deposited by epitaxial growth on exposed portions of the gate and drift layers.  
     
     
         35 . The method of  claim 25 , wherein the source layer is deposited on the channel layer.  
     
     
         36 . The method of  claim 25 , wherein the source layer is deposited by epitaxial growth on the channel layer.  
     
     
         37 . The method of  claim 25 , wherein the source layer is implanted in the channel layer.  
     
     
         38 . The method of  claim 25 , wherein the drift layer is on a buffer layer comprising a semiconductor material of the first conductivity type and wherein the buffer layer is on the semiconductor substrate.