Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production

Abstract

A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

1 . An integrated circuit arrangement comprising: 
 a reference operating potential line operable to carry a basic potential during operation of the circuit arrangement;    a positive operating potential line operable to carry a more positive potential in comparison with the basic potential during operation of the circuit arrangement; and    a capacitor connected between the operating potential lines, said capacitor including the following regions: 
 a basic doping region doped in accordance with a basic doping with a basic doping type and including a region with a maximum dopant concentration;  
 at least one connection region doped in accordance with a connection doping with the basic doping type, the maximum dopant concentration of said connection region being higher than the maximum dopant concentration in the basic doping region;  
 an electrode region arranged at a distance from the basic doping region; and  
 a dielectric arranged between the electrode region and the basic doping region;  
   in which either given an n-type basic doping type the connection region is electrically conductively connected to the positive operating potential line and the electrode region is electrically conductively connected to the reference operating potential line,    or in which case given a p-type basic doping type the connection region is electrically conductively connected to the reference operating potential line and the electrode region is electrically conductively connected to the positive operating potential line    
     
     
         2 . The circuit arrangement of  claim 1 , wherein the electrode region is doped with a maximum dopant concentration of greater than 1×10 18  dopant atoms per cubic centimeter or in that the electrode region includes a metallic region at its side facing the dielectric.  
     
     
         3 . The circuit arrangement of  claim 2 , wherein the electrode region is doped with a maximum dopant concentration of greater than 1×10 18  dopant atoms per cubic centimeter at a side facing the dielectric.  
     
     
         4 . The circuit arrangement of  claim 1 , further comprising an auxiliary doping region doped in accordance with an auxiliary doping with the basic doping type arranged between the basic doping region and the dielectric, the maximum dopant concentration of said auxiliary doping region being equal to the maximum dopant concentration in the basic doping region or the maximum dopant concentration of said auxiliary doping region being greater than the maximum dopant concentration in the basic doping region.  
     
     
         5 . The circuit arrangement of  claim 4 , wherein the maximum dopant concentration of the auxiliary doping region is at least twice as high as the maximum dopant concentration in the basic doping region, and the maximum dopant concentration of the auxiliary doping region is at most half as high as the maximum dopant concentration in the connection region.  
     
     
         6 . The circuit arrangement of  claim 4 , further comprising at least one further connection region arranged in a manner adjoining the basic n-type doping region, the basic p-type doping region or the auxiliary doping region arranged between the connection regions, and a metallic line connecting the connection regions.  
     
     
         7 . The circuit arrangement of  claim 1 , wherein the connection region is arranged in a self-aligning manner neither with respect to the electrode region or with respect to a spacer element arranged on the electrode region.  
     
     
         8 . The circuit arrangement of  claim 4 , wherein the auxiliary doping region adjoins the connection region or an extension region formed at the connection region, or wherein in that the auxiliary doping region is formed only at a central region of the dielectric and not in an edge region of the dielectric, part of the basic doping region arranged at the edge region.  
     
     
         9 . An integrated circuit arrangement comprising: 
 two operating potential lines that carry potentials that are different from one another during operation of the circuit arrangement; and    a capacitor connected between the operating potential lines, said capacitor including: 
 a basic doping region doped in accordance with a basic doping type;  
 at least one doped connection region, the maximum dopant concentration of which is higher than the maximum dopant concentration in the basic doping region;  
 an electrode region arranged at a distance from the basic doping region; and  
 a dielectric arranged between the electrode region and the basic doping region;  
   the dielectric, in a region near the connection region, being at least twice as thick as in a central region of the dielectric.    
     
     
         10 . The circuit arrangement of  claim 9 , further comprising at least one spacer element arranged laterally with respect to the electrode region, the thicker region of the dielectric adjoining the spacer element.  
     
     
         11 . The circuit arrangement of  claim 9 , wherein the connection region is doped in accordance with the basic doping type, or in that the connection region is doped in accordance with a different doping type than the basic doping type.  
     
     
         12 . The circuit arrangement of  claim 9 , wherein the thick dielectric is thinner than 100 nanometers, and in that the circuit arrangement includes at least one field effect transistor whose dielectric has the thickness of the thin dielectric, and includes at least one field effect transistor whose dielectric has the thickness of the thick dielectric.  
     
     
         13 . The circuit arrangement of  claim 12 , wherein the silicide regions are arranged at the connection regions, a silicon region not covered with a silicide region lying between the silicide regions.  
     
     
         14 . The circuit arrangement of  claim 10 , wherein at least one of: 
 the operating potential lines lead to connections via which an external operating voltage is applied during operation of the circuit arrangement;    the basic doping region is formed as a well that is arranged in a substrate doped in accordance with a different doping type than the basic doping region; and    the capacitor comprises a planar component arranged in a plane arranged parallel to at least one metallization layer of the integrated circuit arrangement.    
     
     
         15 . A method for the production of a circuit arrangement comprising a capacitor, the method comprising: 
 forming a basic doping region of a capacitor, doped in accordance with a basic doping type;    forming a connection region of the capacitor, forming a dielectric of the capacitor;    forming an electrode region of the capacitor, said electrode region being spaced apart from the basic doping region, forming a reference operating potential line, which carries a basic potential during operation of the circuit arrangement, and which is electrically conductively connected to the electrode region given an n-type basic doping type, or which is electrically conductively connected to the connection region given a p-type basic doping type,    forming a positive operating potential line, which carries a more positive potential in comparison with the basic potential during operation of the circuit arrangement, and which is electrically conductively connected to the connection region given an n-type basic doping type, or which is electrically conductively connected to the electrode region given a p-type basic doping type.    
     
     
         16 . The method of  claim 15 , further comprising producing the connection region with a dedicated mask step, 
 and forming an auxiliary doping region of the capacitor, which is doped in accordance with the basic doping type and when the maximum of the dopant concentration is equal to or higher than the maximum of the dopant concentration in the basic doping region.    
     
     
         17 . The method for the production of a circuit arrangement comprising a capacitor, the method comprising: 
 forming a basic doping region of a capacitor, doped in accordance with a basic doping type, forming a connection region of the capacitor;    forming a thin dielectric of the capacitor in a central region of the dielectric of the capacitor;    forming a dielectric that is at least twice as thick in comparison with the thin dielectric of the capacitor in an edge region of the dielectric of the capacitor;    forming an electrode region of the capacitor, said electrode region being spaced apart from the basic doping region.    
     
     
         18 . The method of  claim 17 , further comprising: 
 forming two operating potential lines that carry potentials that are different from one another during operation of the circuit arrangement, one operating potential line electrically conductively connected to the connection region and the other operating potential lines electrically conductively connected to the electrode region.    
     
     
         19 . The method of  claim 17 , further comprising producing the dielectric prior to forming a spacer element at the electrode region of the capacitor.  
     
     
         20 . The method  claim 17 , further comprising forming the thin dielectric simultaneously with a layer of the thick dielectric that is near the basic doping region or prior to forming the thick dielectric, or forming the thin dielectric after forming a layer of the thick dielectric that is near the basic doping region.  
     
     
         21 . An integrated circuit arrangement comprising: 
 means for carrying potentials that are different from one another during operation of the circuit arrangement; and    means for storing electrical energy connected between the operating potential lines, said means for storing electrical energy including: 
 a basic doping region doped in accordance with a basic doping type;  
 at least one doped connection region, the maximum dopant concentration of which is higher than the maximum dopant concentration in the basic doping region;  
 an electrode region arranged at a distance from the basic doping region; and  
 a dielectric arranged between the electrode region and the basic doping region;  
   the dielectric, in a region near the connection region, being at least twice as thick as in a central region of the dielectric.    
     
     
         22 . The circuit arrangement of  claim 21 , further comprising at least one spacer element arranged laterally with respect to the electrode region, the thicker region of the dielectric adjoining the spacer element.  
     
     
         23 . The circuit arrangement of  claim 21 , wherein the connection region is doped in accordance with the basic doping type, or in that the connection region is doped in accordance with a different doping type than the basic doping type.  
     
     
         24 . The circuit arrangement of  claim 21 , wherein the thick dielectric is thinner than 100 nanometers, and in that the circuit arrangement includes at least one field effect transistor whose dielectric has the thickness of the thin dielectric, and includes at least one field effect transistor whose dielectric has the thickness of the thick dielectric.