Gapped-plate capacitor

Abstract

In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

1 . A storage device, comprising: 
 an oxide layer;    a bottom electrode under said oxide layer; and    a top plate over said oxide layer and further comprising:    a first portion over said bottom electrode and defining a first cavity.    
   
   
       2 . The storage device in  claim 1 , wherein said top plate further comprises a second portion defining a second cavity.  
   
   
       3 . The storage device in  claim 2 , wherein said second cavity is a slit and intersects said first cavity.  
   
   
       4 . The storage device in  claim 3 , wherein said second cavity intersects said first cavity at an angle of generally 90 degrees.  
   
   
       5 . The storage device in  claim 4 , wherein said first cavity is a slit.  
   
   
       6 . The storage device of  claim 1 , wherein the top plate has a thickness T and further comprising: 
 a first conductive portion defining said thickness T,    a second conductive portion having said thickness T and physically coupled to said first conductive portion in a first area and physically separated from said first conductive portion by a gap space S in a second area;    the oxide under said top plate defining a height H; and    a substrate under said oxide;    wherein said gap space S is sized to allow a capacitance greater than a similar capacitor having no gap space S, and wherein, for a cross section of said capacitor that includes said gap space S, a following formula is true:        H* 2.434*( T/H ) 0.222   >S.     
   
   
       7 . The storage device of  claim 6 , wherein said height H is 0.01 microns, and said thickness T is 0.27 microns.  
   
   
       8 . The storage device of  claim 7;  wherein said gap space S is generally less than 0.0506 microns.  
   
   
       9 . The storage device of  claim 1 , wherein the bottom electrode includes a hemispherical grain surface.  
   
   
       10 . The storage device of  claim 1 , wherein the top plate includes tungsten.  
   
   
       11 . The storage device of  claim 1 , wherein the top plate includes tungsten silicide.  
   
   
       12 . The storage device of  claim 11 , wherein the top plate includes polysilicon.  
   
   
       13 . A capacitor, comprising: 
 a substrate;    a patterned conductive layer over said substrate, including a first hole;    an oxide between said substrate and said patterned conductive layer and within said first hole.    
   
   
       14 . The capacitor in  claim 13;  wherein said patterned conductive layer has a second hole shaped differently from said first hole.  
   
   
       15 . The capacitor of  claim 14 , wherein the patterned conductive layer includes tungsten.  
   
   
       16 . The capacitor of  claim 14 , wherein the patterned conductive layer includes tungsten silicide.  
   
   
       17 . The capacitor of  claim 16 , wherein the patterned conductive layer includes polysilicon.  
   
   
       18 . A capacitor, comprising: 
 a first electrically conductive plate having a first portion;    a second electrically conductive plate, further comprising: 
 a second portion generally parallel to said first portion of said first electrically conductive plate and configured to allow for parallel capacitance in cooperation with said first electrically conductive plate, and  
 a third portion defining a primary slot within said second electrically conductive plate and configured to allow for fringe capacitance in cooperation with said first portion of said first electrically conductive plate, wherein said fringe capacitance is at least equal to said parallel capacitance per a unit of measurement; and  
   a dielectric between said first electrically conductive plate and said second electrically conductive plate and within said primary slot.    
   
   
       19 . The capacitor in  claim 18 , wherein said second electrically conductive plate is under said first electrically conductive plate.  
   
   
       20 . The capacitor in  claim 19 , wherein said second electrically conductive plate further comprises a substrate.  
   
   
       21 . The capacitor in  claim 20;  wherein said first electrically conductive plate further comprises a fourth portion defining a secondary slot within said first electrically conductive plate and configured to allow for fringe capacitance in cooperation with said second electrically conductive plate that is at least equal to said parallel capacitance per said unit of measurement.  
   
   
       22 . The capacitor in  claim 21 , wherein said primary slot defines an axis generally perpendicular to said first portion of said first electrically conductive plate.  
   
   
       23 . A semiconductor device, comprising: 
 a substrate;    an oxide over said substrate; and    a conductive layer over said oxide, wherein said conductive layer and said substrate are configured to generate a parallel capacitance, and wherein a selection of said substrate and said conductive layer is untextured and defines a gap associated with a fringe capacitance that is at least as great as said parallel capacitance per a unit of width.    
   
   
       24 . The semiconductor device in  claim 23 , wherein said substrate is generally free of microstructures and defines said gap.  
   
   
       25 . A capacitor, comprising: 
 a dielectric layer;    a first plate on one side of said dielectric layer; and    a second plate on another side of said dielectric layer and defining a generally continuous surface and a discontinuity at said surface, wherein said surface is configured to generate parallel capacitance with said first plate and said discontinuity is configured to generate fringe capacitance with said first plate.    
   
   
       26 . The capacitor in  claim 25 , wherein: 
 said first plate is planar;    said generally continuous surface is a planar surface parallel to said first plate; and    said discontinuity is nonparallel to said first plate.    
   
   
       27 . The capacitor in  claim 26 , wherein said discontinuity is vertically offset from said first plate.  
   
   
       28 . The capacitor in  claim 27 , wherein said discontinuity is perpendicular to said first plate.