Method and apparatus for testing bumped die

Abstract

An apparatus for testing unpackaged semiconductor dice having raised ball contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the ball contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

1 . A bump substrate for use during the testing of a semiconductor die having bond pads having raised contact bumps thereon extending above a surface of the semiconductor die comprising: 
 a bump substrate having a plurality of contact bump receiving sites formed therein, each of the plurality of contact bump receiving sites having a plurality of sidewalls and a bottom and having a plurality of conductive traces located on at least portions of the plurality of sidewalls thereof for contacting a plurality of conductive traces on the bump substrate and for contacting a corresponding raised contact bump of the raised contact bumps on the bond pads received at the plurality of contact bump receiving sites, a conductive trace of the plurality of conductive traces extending along at least a portion of a sidewall of the plurality of sidewalls of a contact bump receiving site of the plurality of contact bump receiving sites and at least one other conductive trace of the plurality of conductive traces extending along at least a portion of another sidewall of the plurality of sidewalls and a portion of the bottom of the contact bump receiving site of the plurality of contact bump receiving sites, the plurality of conductive traces forming a plurality of rows and a plurality of columns interconnecting each contact bump receiving site of the plurality of contact bump receiving sites to at least one adjacent contact bump receiving site of the plurality of contact bump receiving sites in an adjacent row of the plurality of rows and an adjacent column of the plurality of columns.    
   
   
       2 . The bump substrate according to  claim 1 , wherein the plurality of contact bump receiving sites comprise pits fabricated in the bump substrate, each pit of the pits having opposing walls wherein the plurality of conductive traces extend down the opposing walls and are free from contact with each other.  
   
   
       3 . A bump plate fabricated to receive a plurality of contact bumps on a semiconductor die, comprising: 
 a plurality of contact receiving sites, said plurality of sites fabricated in said bump plate to correspond to a pattern established by a said plurality of contact bumps on said semiconductor die;    a plurality of a metal traces, for each site of said plurality of contact sites, to contact with a corresponding contact bump of said plurality of contact bumps received at said contact site.    
   
   
       4 . The bump plate according to  claim 3 , wherein said plurality of metal traces form a conduction array of rows and columns interconnecting each contact site to at least one adjacent contact site of said plurality of sites  
   
   
       5 . The bump plate according to  claim 3 , wherein said plurality of contact sites are a plurality of pits fabricated in a semiconductor substrate having opposing walls wherein said metal traces extend down said opposing walls, but do not contact one another.  
   
   
       6 . The bump plate according to  claim 3 , wherein said contact sites are comprised of: 
 a plurality of risers, over which said such plurality of metal traces extend; and    a plurality of blades, situated between the said plurality of rises, to pierce an oxide layer on said contact bump.    
   
   
       7 . The bump plate according to  claim 3 , wherein said contact location is comprised of: 
 a plurality of retaining posts, over each of which extends one of said metal traces and in which a bump seat is formed for receiving said contact bump.    
   
   
       8 . A bump plate in a semiconductor substrate fabricated to receive a plurality of contact bumps on a semiconductor die, fabricated according to the following process steps: 
 forming a plurality of contact bump receiving sites in said bump plate to correspond to a pattern established by a said plurality of contact bumps on said semiconductor die, at least one of said plurality of contact bump receiving sites having a plurality sidewalls; and    forming a plurality of a conductive traces on said substrate and said sidewalls, for at least one contact site of said plurality of contact bump receiving sites, to contact with a corresponding contact bump of said plurality of contact bumps received at said contact site.    
   
   
       9 . The bump plate according to  claim 8 , wherein said contact bump receiving site forming step comprises: 
 applying a photo resist layer on said substrate;    exposing selected regions of said photo resist layer;    removing said exposed photo resist layer regions; and,    etching said removed regions to form said sidewalls in each of said plurality of contact receiving sites.    
   
   
       10 . The bump plate according to  claim 8 , wherein said conductive trace forming step comprises: 
 applying a photo resist layer to said substrate;    exposing selected regions of said photo resist layer to form conductive trace patterns on said substrate;    removing said exposed photo resist layer regions; and.    forming a metal trace in said removed photo resist layer regions extending down each of said sidewalls of said plurality of contact receiving sites.    
   
   
       11 . The bump plate according to  claim 8 , wherein said plurality of conductive traces form a conduction array of rows and columns interconnecting each contact site to at least one adjacent contact site.  
   
   
       12 . The bump plate according to  claim 8 , wherein said contact sites are pits fabricated in a semiconductor substrate having opposing walls wherein said metal traces extend down said opposing walls, but do not contact one another.  
   
   
       13 . The bump plate according to  claim 8 , wherein said contact sites forming site comprises the steps of: 
 applying a photo resist layer on said substrate;    exposing selected regions of said photo resist layer;    removing said exposed photo resist layer regions;    forming a plurality of risers in said removed regions; and,    forming a plurality of blades, situated between said plurality of risers.    
   
   
       14 . The bump plate according to  claim 13 , wherein said conductive trace forming step comprises: 
 applying a photo resist layer to said substrate;    exposing selected regions of said photo resist layer to form conductive trace patterns on said substrate;    removing said exposed photo resist layer regions; and.    forming a metal trace in said removed photo resist layer regions extending over each of said plurality of risers.    
   
   
       15 . The bump plate according to  claim 8 , wherein said contact sites forming site comprises the steps of: 
 applying a photo resist layer on said substrate;    exposing selected regions of said photo resist layer;    removing said exposed photo resist layer regions; and    forming a plurality of retaining posts in said removed regions.    
   
   
       16 . The bump plate according to  claim 15 , wherein said conductive trace forming step comprises: 
 applying a photo resist layer to said substrate;    exposing selected regions of said photo resist layer to form conductive trace patterns on said substrate;    removing said exposed photo resist layer regions; and.    forming a metal trace in said removed photo resist layer regions extending over each of said plurality of retaining posts.