Packaged die on PCB with heat sink encapsulant and methods

Abstract

An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

1 . An assembly method for a semiconductor assembly having a substrate and a semiconductor chip having a first surface and a second surface comprising: 
 attaching at least a portion of the first surface of the semiconductor chip to at least a portion of the substrate;    forming an electrical connection between the semiconductor chip and the substrate;    forming a wall substantially around a periphery of the second surface of the semiconductor chip using a barrier material, the wall around the periphery of the second surface of the semiconductor chip defining a recess, the barrier material having a first thermal conductivity;    extending the barrier material to contact the substrate; and    disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.    
     
     
         2 . The method of  claim 1 , wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.  
     
     
         3 . The method of  claim 1 , wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         4 . The method of  claim 1 , wherein the barrier material substantially encapsulates the at least one bond wire.  
     
     
         5 . The method of  claim 1 , wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         6 . The method of  claim 5 , wherein the barrier material substantially encapsulates the at least one tape automated bond.  
     
     
         7 . The method of  claim 1 , wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         8 . The method of  claim 7 , further comprising disposing an underfill encapsulant substantially between the semiconductor chip and the substrate.  
     
     
         9 . A method of making a semiconductor assembly having a substrate and a plurality of semiconductor chips, each semiconductor chip of the plurality having a first surface and a second surface, comprising: 
 attaching a portion of the first surface of each semiconductor chip to a portion of the substrate;    disposing an underfill material substantially between the substrate and each semiconductor chip;    forming an electrical connection between each semiconductor chip and the substrate;    forming a wall substantially around a periphery of the second surface of each semiconductor chip using a barrier material, the wall and the second surface of each semiconductor chip defining a recess, the barrier material having a first thermal conductivity;    extending the barrier material to contact and adhere to the substrate; and    disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.    
     
     
         10 . The method of  claim 9 , wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.  
     
     
         11 . The method of  claim 9 , wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         12 . The method of  claim 11 , wherein the barrier material substantially encapsulates the at least one bond wire.  
     
     
         13 . The method of  claim 11 , wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         14 . The method of  claim 13 , wherein the barrier material substantially encapsulates the at least one tape automated bond.  
     
     
         15 . The method of  claim 9 , wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         16 . A heat transfer method for a semiconductor assembly having a substrate and a plurality of semiconductor chips, each semiconductor chip of the plurality having a first surface and a second surface, comprising: 
 attaching a portion of the first surface of each semiconductor chip to a portion of the substrate;    disposing an underfill material substantially between the substrate and each semiconductor chip;    forming an electrical connection between each semiconductor chip and the substrate;    forming a wall substantially around a periphery of the second surface of each semiconductor chip using a barrier material, the wall and the second surface of each semiconductor chip defining a recess, the barrier material having a first thermal conductivity;    extending the barrier material to contact and adhere to the substrate; and    disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.    
     
     
         17 . The method of  claim 16 , wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.  
     
     
         18 . The method of  claim 16 , wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         19 . The method of  claim 18 , wherein the barrier material substantially encapsulates the at least one bond wire.  
     
     
         20 . The method of  claim 18 , wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.  
     
     
         21 . The method of  claim 20 , wherein the barrier material substantially encapsulates the at least one tape automated bond.  
     
     
         22 . The method of  claim 16 , wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.