Integrated circuit capacitor structure

Abstract

Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

1 . A method for forming a metal-insulator-metal capacitor in a semiconductor process, the method comprising: 
 forming an insulating layer on a semiconductor substrate;    forming a first connection wire and a second connection wire;    forming a bottom electrode on the insulating layer and disposed over the first connection wire;    forming a dielectric layer over the bottom electrode;    forming a top electrode disposed over the bottom electrode; and    forming a contact from the second connection wire to a bottom surface of the top electrode.    
   
   
       2 . The method of  claim 1 , wherein forming the first and second connection wire comprises: 
 forming a first and a second trench in the insulating layer;    forming a metal layer within the first trench and the second trench; and    planarizing the metal layer to form a first connection wire in the first trench and a second connection wire in the second trench.    
   
   
       3 . The method of  claim 2 , further comprising forming a barrier layer in the first and second trenches prior to forming the metal layer within the first and second trenches.  
   
   
       4 . The method of  claim 3  wherein forming a barrier layer comprises forming a layer from a material selected from a group consisting essentially of a transition metal, a transition metal alloy, a transition metal compound, and any combination thereof.  
   
   
       5 . The method of  claim 2  wherein forming the metal layer comprises forming a copper layer.  
   
   
       6 . The method of  claim 1 , wherein forming the first and second connection wire comprises: 
 forming a conductive layer on the insulating layer;    patterning the conductive layer to form a first wire connection and a second wire connection;    depositing an interlayer dielectric layer on the first and second wire connections; and    planarizing the first and second wire connections and the interlayer dielectric layer.    
   
   
       7 . The method of  claim 6  wherein planarizing the first and second wire connections and the interlayer dielectric layer comprises perfonning a CMP process.  
   
   
       8 . The method of  claim 1 , wherein forming the first and second connection wire comprises: 
 forming a conductive layer on the insulating layer; and    patterning the conductive layer to form a first wire connection and a second wire connection.    
   
   
       9 . A method for forming a metal-insulator-metal capacitor in a semiconductor process, the method comprising: 
 forming an insulating layer on a semiconductor substrate;    forming a first wire connection and a second wire connection;    forming a first interlayer dielectric layer on the first wire connection and the second wire connection;    forming a first contact hole in the first interlayer dielectric layer to expose the first wire connection;    forming a bottom electrode on the first interlayer dielectric layer and within the first contact hole to contact the first wire connection;    forming a dielectric layer on the bottom electrode;    forming a second contact hole in the dielectric layer and in the first interlayer dielectric layer to contact the second wire connection; and    forming a top electrode disposed over the bottom electrode and within the second contact hole to contact the second wire connection.    
   
   
       10 . The method of  claim 9 , wherein forming the first and second wire connection comprises: 
 forming a first and a second trench in the insulating layer;    forming a conductive layer within the first trench and the second trench; and    planarizing the conductive layer to form a first wire connection in the first trench and a second wire connection in the second trench.    
   
   
       11 . The method of  claim 9 , wherein forming the first and second connection wire comprises: 
 forming a conductive layer on the insulating layer;    patterning the conductive layer to form a first wire connection and a second wire connection;    depositing an interlayer dielectric layer on the first and second wire connections; and    planarizing the first and second wire connections and the interlayer dielectric layer.    
   
   
       12 . The method of  claim 9 , wherein forming the first and second wire connection comprises: 
 forming a conductive layer on the insulating layer; and    patterning the conductive layer to form a first wire connection and a second wire connection.    
   
   
       13 . The method of  claim 9  wherein forming the first contact hole comprises forming a plurality of separate contact holes.  
   
   
       14 . The method of  claim 9  wherein forming the second contact hole comprises forming a second plurality of separate contact holes.  
   
   
       15 . A method for forming a metal-insulator-metal capacitor in a semiconductor process, the method comprising: 
 forming an insulating layer on a semiconductor substrate;    forming a first wire connection and a bottom electrode;    forming a dielectric layer on the first wire connection and the bottom electrode;    forming a first contact hole in the dielectric layer and disposed over the first wire connection;    forming a top electrode disposed over the dielectric layer and within the first contact hole to contact the first wire connection;    forming a interlayer dielectric layer disposed over the top electrode, the dielectric layer, and the bottom electrode;    forming a second contact hole in the interlayer dielectric layer and in the dielectric layer to expose the bottom electrode; and    forming a contact plug within the second contact hole and structured to contact a top surface of the bottom electrode.    
   
   
       16 . The method of  claim 15 , wherein forming the first wire connection and the bottom electrode comprises: 
 forming a first and a second trench in the insulating layer;    forming a conductive layer within the first trench and the second trench; and    planarizing the conductive layer to form a first wire connection in the first trench and a bottom electrode in the second trench.    
   
   
       17 . The method of  claim 15 , wherein forming the first wire connection and the bottom electrode comprises: 
 forming a conductive layer on the insulating layer;    patterning the conductive layer to form a first wire connection and a bottom electrode;    depositing an interlayer dielectric layer on the first wire connection and the bottom electrode; and    planarizing the first wire connection, the bottom electrode, and the interlayer dielectric layer.    
   
   
       18 . The method of  claim 15 , wherein forming the first wire connection and the bottom electrode comprises: 
 forming a conductive layer on the insulating layer; and    patterning the conductive layer to form a first wire connection and a bottom electrode.    
   
   
       19 . A method for forming a metal-insulator-metal capacitor in a semiconductor process and on a semiconductor substrate having an insulating layer formed thereon, the method comprising: 
 forming a connection line on the insulating layer;    forming a bottom electrode on the insulating layer;    forming a capacitor dielectric layer disposed on the bottom electrode;    forming a top electrode disposed on the capacitor dielectric layer; and    coupling the connection line to a bottom surface of the top electrode.    
   
   
       20 . The method of  claim 19  wherein forming the connection line comprises: 
 forming a first and second trench in the insulating layer;    forming a barrier layer in the first and second trench;    forming a metal layer on the barrier layer; and    planarizing the metal layer.    
   
   
       21 . The method of  claim 18  wherein forming a metal layer comprises electroplating the barrier layer.  
   
   
       22 . The method of  claim 18  wherein forming a barrier layer comprises forming a layer including titanium.  
   
   
       23 . The method of  claim 19  wherein forming the connection line comprises: 
 forming a metal layer on the insulating layer;    patterning the metal layer to form a connection line;    forming a second insulating layer on the connection line; and    planarizing the metal layer and the second insulating layer by chemical-mechanical-polishing.