Selective solder deposition by self-assembly of nano-sized solder particles, and methods of assembling soldered packages

Abstract

A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.

1 . A substrate comprising: 
 a bond pad;    a bond-pad resist area; and    a solder suspension disposed on the bond pad, wherein the solder suspension exhibits macroscopic surface tension, wherein the solder suspension has a solid phase including a particle size distribution of about 50% passing 20 nm, and wherein the bond pad is solder-suspension philic and the solder-resist area is solder-suspension phobic.    
   
   
       2 . The substrate of  claim 1 , wherein the solder suspension includes a liquid phase, and wherein a flux is intermingled in the liquid phase, selected from solution with the liquid phase, at least partially reacted with the liquid phase, and mixed with the liquid phase.  
   
   
       3 . The substrate of  claim 1 , wherein the solid phase is selected from copper, silver, gold, lead, tin, and combinations thereof.  
   
   
       4 . The substrate of  claim 1 , wherein the solder suspension includes a percent solids in a range from about 30% to about 90%.  
   
   
       5 . The substrate of  claim 1 , wherein the bond pad is one in a plurality of bond pads, wherein each bond pad includes an edge dimension from about 50 μm to about 150 μm, wherein the bond-pad resist area is disposed between any two adjacent bond pads that share an edge border, and wherein the bond pads are spaced upon the bond-pad resist area, and where a bond pad has an edge-dimension of unity, two adjacent bond pads are spaced on centers having a dimension of about 1.5 times unity.  
   
   
       6 . A package comprising: 
 a substrate; and    a solder on the substrate, wherein the reflowed solder includes a grain size in a range of less than or equal to about 20 micrometer (μm).    
   
   
       7 . The package of  claim 6 , wherein the substrate includes a microelectronic die.  
   
   
       8 . The package of  claim 6 , wherein the substrate includes a second-level mounting substrate.  
   
   
       9 . The package of  claim 6 , wherein the substrate includes a first-level board.  
   
   
       10 . A computing system comprising: 
 a microelectronic die disposed upon a substrate;    a solder bump that couples the microelectronic die to the substrate, the solder bump including: 
 a metal including a grain size including about 50% smaller than about 20 nm, and wherein the metal includes a melting temperature equal to or below about 400° C.; and  
 a dynamic random access data storage device coupled to the die.  
   
   
   
       11 . The computing system of  claim 10 , wherein the system is disposed in one of a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.  
   
   
       12 . The computing system of  claim 10 , wherein the microelectronic die is selected from a data storage device, a digital signal processor, a micro controller, an application specific integrated circuit, and a microprocessor.