Methods, Apparatus and Computer Program Products for Generating Selective Netlists that Include Interconnection Influences at Pre-Layout and Post-Layout Design Stages

Abstract

Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein. These embodiments may also be configured to generate a layout schematic from the first schematic of the integrated circuit and generate parasitic resistances and capacitances of the post-layout interconnects that extend between a plurality of cells in the layout schematic. Operations are then performed to generate parasitic resistances and capacitances of interconnects internal to at least one cell in the layout schematic.

1 . A selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the device comprising: 
 a schematic circuit generation unit for generating a schematic circuit in response to input information including information on circuit devices included in respective cells, information on connections between the circuit devices, and schematic layout information of the cells; and    a selective netlist output unit for selecting at least one cell included in the schematic circuit and generating a netlist of the selected cell, in response to selection information.    
   
   
       2 . A selective netlist generation device for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the device comprising: 
 a selective netlist processor for generating a selective netlist of a schematic circuit including cells, a first simulation schematic circuit obtained by combining the schematic circuit and an interconnection schematic circuit, a second simulation schematic circuit obtained by combining the schematic circuit and a schematic circuit corresponding to a netlist of parasitic resistance and parasitic capacitance, and cells performing specific operations of the simulation schematic circuit, in response to input information including information on circuit devices included in the respective cells, information on connections between the circuit devices, and schematic layout information of the cells, information the interconnections interconnecting the cells, and selection information for selecting cells performing specific operations among the cells;    an interconnection generator for generating the interconnections in response to positional information of the cells included in the schematic circuit provided from the selective netlist processor and providing the generated information on the interconnections;    a layout generator for generating a layout of the semiconductor integrated circuit in response to the information on the schematic circuit provided from the selective netlist processor; and    a parasitic RC extractor for extracting a netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the interconnections, generated from the layout generator, and providing the extracted netlist to the selective netlist processor.    
   
   
       3 . The device as claimed in  claim 2 , wherein the selective netlist generation device combines the selective netlist of the parasitic resistance and parasitic capacitance, which are parasitic on the layout of the cells extracted by the parasitic RC extractor and the selective netlist of the selected cells to generate a combined selective netlist.  
   
   
       4 . The device as claimed in  claim 3 , wherein the selective netlist processor comprises: 
 a schematic circuit generation unit for generating the schematic circuit in response to the input information;    a first interconnection schematic circuit generation unit for generating the schematic circuit of the interconnections in response to the information on the interconnections;    a second interconnection schematic circuit generation unit for generating the schematic circuit of the interconnection layout in response to the netlist of the parasitic resistance and parasitic capacitance;    a simulation schematic circuit generation unit for combining first ports included in the cells of the schematic circuit and second ports of the interconnection schematic circuit corresponding to the first ports to generate and store the first simulation schematic circuit, and combining the first ports included in the cells of the schematic circuit and the second ports of the schematic circuit of the interconnection layout corresponding to the first ports, wherein the stored first simulation schematic circuit is replaced by the generated second simulation schematic circuit; and    a selective netlist output unit for selecting cells performing specific operations of the replaced simulation schematic circuit and generating a selective netlist of the selected cells.    
   
   
       5 . The device as claimed in  claim 4 , wherein the schematic circuit generated by the first interconnection schematic circuit generating circuit maintains positional relations between the cells and includes a hybrid π model.  
   
   
       6 . The device as claimed in  claim 5 , wherein the schematic circuit generated by the second interconnection schematic circuit has a tree structure.  
   
   
       7 . The device as claimed in  claim 6 , wherein non-selected cells connected to the cells selected by the selection information via the interconnections are used as capacitance devices.  
   
   
       8 . A method for generating a selective netlist, which is required to simulate a specific part of a semiconductor integrated circuit, the method comprising: 
 (a) generating a schematic circuit in response to input information including information on circuit devices included in respective cells, information on connections between the circuit devices, and schematic layout information of the cells; and    (b) selecting at least one cell included in the schematic circuit and generating a netlist of the selected cell, in response to selection information.