Method of manufacturing split gate type nonvolatile memory device

Abstract

A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.

1 . A method comprising: 
 depositing a conductive layer over a floating gate; and    forming a control gate which is over only a portion of the floating gate by dry etching the conductive layer.    
   
   
       2 . The method of  claim 1 , wherein the floating gate and the control gate are part of a split gate transistor.  
   
   
       3 . The method of  claim 2 , wherein the split gate transistor is part of a nonvolatile memory device.  
   
   
       4 . A method of manufacturing a split gate type semiconductor memory device, comprising: 
 forming a gate insulating film and a conductive layer on a semiconductor substrate;    forming mask patterns on the conductive layer which define at least a pair of first openings that expose the conductive layer;    forming intergate oxide films by selective thermal oxidation of the conductive layer exposed by the mask patterns;    forming a conformal capping oxide film on the mask patterns and the intergate oxide film;    exposing a portion of the mask pattern by removing a portion of the capping oxide film disposed between the intergate oxide films;    removing the mask patterns exposed by using the remaining capping oxide film as an etch mask;    removing the remaining capping oxide film;    forming spacers on inner walls of the second opening;    defining a third opening by etching the conductive layer, exposing the gate insulating film, by using the mask patterns, the spacers, and the intergate oxide films as etch masks;    forming a source region by ionic implanting a dopant into the third opening;    forming an insulating film plug by filling the third opening;    exposing side faces of the insulating film plug by removing the mask patterns and the spacers;    forming a pair of floating gates by dry etching portions of the conductive layer using the intergate oxide films as an etch mask to expose the gate insulating film;    forming tunnel insulating films on the side walls of each floating gate;    forming a spacer type control gate by self aligning on side walls of the insulating film plug; and, p 1  forming a drain region in the semiconductor substrate near an outer region of the control gate.    
   
   
       5 . The method of  claim 4 , wherein the conductive layer and the control gate are formed of doped polysilicon.  
   
   
       6 . The method of  claim 4 , wherein the mask patterns are formed of a silicon nitride film.  
   
   
       7 . The method of  claim 4 , wherein the-integrate oxide films are formed with a thickness in an approximate range of 500˜2,000 Å.  
   
   
       8 . The method of  claim 4 , wherein the spacers and the mask patterns are formed of the same material.  
   
   
       9 . The method of  claim 4 , wherein the mask patterns and the spacers are formed of silicon nitride and a phosphoric acid strip is used to remove the mask patterns and the spacers.  
   
   
       10 . The method of  claim 4 , wherein the formation of the source region comprises: 
 implanting a dopant into the third opening; and,    driving-in the implanted dopant by heat treatment, and    while performing the heat treatment, sealing side walls of the conductive layer in the third opening with a thermal oxide film.    
   
   
       11 . The method of  claim 4 , wherein the formation of the insulating film plug comprises: 
 forming a gap fill oxide film to fill completely the third opening; and,    planarizing the gap fill oxide film until a surfaces of the mask patterns are exposed by using a chemical mechanical polishing process.    
   
   
       12 . The method of  claim 4 , wherein the formation of the tunnel insulating film comprises: 
 oxidizing the resultant product having floating gates thermally;    depositing an oxide film on the floating gates; and,    performing a heat treatment to harden the oxide film.    
   
   
       13 . The method of  claim 4 , further comprising: 
 forming an interlayer insulating film;    forming metal plugs connecting to the drain regions through the interlayer insulating film; and,    forming a metal wiring pattern connected to the metal plugs on the interlayer insulating film.