Low-Voltage, Multiple Thin-Gate Oxide and Low-Resistance Gate Electrode

Abstract

A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.

1 . A memory system on a silicon chip, comprising: 
 an array of memory cells on a substrate, memory cells arranged in rows along a first direction and columns along a second direction, a memory cell having a floating gate separated from the substrate by a first dielectric layer of a first thickness, adjacent floating gates along a row separated by shallow trench isolation structures, floating gates limited in the first direction by the shallow trench isolation structures so that floating gates do not overlap shallow trench isolation structures;    a high-voltage peripheral circuit having shallow trench isolation structures and devices that include a second dielectric layer of a second thickness;    a low-voltage peripheral circuit having shallow trench isolation structures and devices that include a third dielectric layer of a third thickness;    a conductive layer that extends across the array, high-voltage peripheral circuit and low-voltage peripheral circuit, the conductive layer separated from the floating gates by an inter-layer dielectric, separated from the substrate of the high-voltage peripheral circuit by the second dielectric layer and separated from the substrate of the low-voltage peripheral circuit by the third dielectric layer.