Modification of electrical properties for semiconductor wafers

Abstract

A semiconductor wafer structure. The structure comprises a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer such that no additional wafers of the plurality of semiconductor wafers is located between a topside of the first semiconductor wafer and a backside of the of the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A substructure is formed comprising a material from the plurality of materials existing in the relationship sandwiched between a topside of the first semiconductor wafer and a backside of the of the second semiconductor wafer. The first semiconductor wafer comprises a discrete value from the plurality of values for the electrical characteristic that correlates with the material in said relationship.

1 . An electrical structure, comprising: 
 a plurality of semiconductor wafers, wherein the plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer, wherein the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer; and    a material, wherein the material is located directly between the topside of the first semiconductor wafer and the backside of the of the second semiconductor wafer, wherein a relationship exists between a plurality of values for an electrical characteristic and a plurality of materials comprising the material, and wherein the first semiconductor wafer comprises a discrete value from the plurality of values for the electrical characteristic that correlates with the material in said relationship.    
   
   
       2 . The electrical structure of  claim 1 , wherein the material is attached to the backside of the second semiconductor wafer.  
   
   
       3 . The electrical structure of  claim 1 , wherein the material is selected from the group consisting of Si, Si3N4, and Si02.  
   
   
       4 . The electrical structure of  claim 1 , wherein the electrical characteristic is polysilicon sheet resistance.  
   
   
       5 . The electrical structure of  claim 1 , wherein the electrical characteristic is a gate oxide thickness.  
   
   
       6 . The electrical structure of  claim 1 , wherein said relationship is a graphical relationship.  
   
   
       7 . The electrical structure of  claim 1 , wherein said relationship is a tabular relationship.  
   
   
       8 . The electrical structure of  claim 1 , wherein said discrete value for said first semiconductor wafer is for said topside of said first semiconductor wafer.  
   
   
       9 . The electrical structure of  claim 8 , wherein said discrete value for said first semiconductor wafer is for active components on said topside of said first semiconductor wafer.  
   
   
       10 . The electrical structure of  claim 1 , wherein the material comprises a first material and a second material.  
   
   
       11 . An electrical structure, comprising: 
 a plurality of semiconductor wafers, wherein the plurality of semiconductor wafers comprises a first semiconductor wafer, a second semiconductor wafer, a third semiconductor wafer, and a fourth semiconductor wafer, wherein the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer, wherein the third semiconductor wafer is located directly adjacent to the fourth semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the third semiconductor wafer and a backside of a portion of the fourth semiconductor wafer;    a first material, wherein the first material is located directly between the topside of the first semiconductor wafer and the backside of the of the second semiconductor wafer, wherein a relationship exists between a plurality of values for an electrical characteristic and a plurality of materials, wherein the plurality of materials comprises the first material, and wherein the first semiconductor wafer comprises a first discrete value from the plurality of values for the electrical characteristic that correlates with the first material in said relationship; and    a second material, wherein the second material is located directly between the topside of the third semiconductor wafer and the backside of the of the fourth semiconductor wafer, wherein the plurality of materials comprises the second material, wherein the third semiconductor wafer comprises a second discrete value from the plurality of values for the electrical characteristic that correlates with the second material in said relationship, and wherein the first discrete value is not a same value as the second discrete value.    
   
   
       12 . The electrical structure of  claim 11 , wherein said first material is applied to the backside of the second semiconductor wafer, and wherein the second material is applied to the backside of the fourth semiconductor wafer.  
   
   
       13 . The electrical structure of  claim 11 , wherein said first material is a first monitor wafer placed between the backside of the second wafer and the topside of the first semiconductor wafer, and wherein said second material is a second monitor wafer placed between the backside of the fourth semiconductor wafer and the topside of the third semiconductor wafer.  
   
   
       14 . The electrical structure of  claim 11 , wherein the first material and the second material are each selected from the group consisting of Si, Si3N4, and Si02.  
   
   
       15 . The electrical structure of  claim 11 , wherein the electrical characteristic is polysilicon sheet resistance.  
   
   
       16 . The electrical structure of  claim 11 , wherein the electrical characteristic is a gate oxide thickness.  
   
   
       17 . The electrical structure of  claim 11 , wherein said relationship is a graphical relationship.  
   
   
       18 . The electrical structure of  claim 11 , wherein said relationship is a tabular relationship.  
   
   
       19 . The electrical structure of  claim 11 , wherein said first discrete value for said first semiconductor wafer is for said topside of said first semiconductor wafer, and wherein said second discrete value is for said topside of said third semiconductor wafer.  
   
   
       20 . The electrical structure of  claim 11 , wherein said first discrete value for said first semiconductor wafer is for active components on said topside of said first semiconductor wafer, and wherein said second discrete value for said third semiconductor wafer is for active components on said topside of said third semiconductor wafer.