Isolated fully depleted silicon-on-insulator regions by selective etch

Abstract

The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

1 . A semiconductor structure comprising: 
 at least two insulating pillars atop a substrate;    a layer of Si bridging said at least two insulating pillars; and    a cavity formed between each of said two insulating pillars and underlying said layer of Si, wherein said layer of Si has a uniform thickness of about 10 nm or less.    
   
   
       2 . The semiconductor structure of  claim 1  wherein said layer of Si bringing said at least two insulating pillars further comprises a passivation layer underlying said layer of Si.  
   
   
       3 . The semiconductor structure of  claim 2  wherein said passivation layer has a thickness of 10 nm or less.  
   
   
       4 . The semiconductor structure of  claim 2  wherein said passivation layer is a thermal oxide.  
   
   
       5 . The semiconductor structure of  claim 1  wherein said substrate comprises Si, SiGe, SiGeC, SiC, polysilicon, epitaxial silicon, amorphous Si or combinations thereof.  
   
   
       6 . The semiconductor structure of  claim 1  wherein said two insulating pillars comprise an oxide, nitride or oxynitride.  
   
   
       7 . The semiconductor structure of  claim 1  wherein said cavity is filled with air.  
   
   
       8 . The semiconductor structure of  claim 1  wherein a portion of said layer of Si forms a device channel for a field effect transistor.