Interface circuit and signal clamping circuit using level-down shifter

Abstract

Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

1 . A level down shifter comprising: 
 a first inverter, which is driven by a first power and receives an input signal that swings from ground to a voltage level of a second power;    a second inverter, which is driven by the second power and receives the input signal;    a PMOS transistor whose source is connected to the first power and whose gate is connected to an output of the first inverter; and    an NMOS transistor whose source is connected to ground, whose gate is connected to an output of the second inverter, and whose drain is connected to a drain of the PMOS transistor.    
   
   
       2 . The level-down shifter of  claim 1 , wherein a voltage level of the second power is higher than the voltage level of the first power.  
   
   
       3 . An interface circuit comprising: 
 a first power circuit having an input and an output, powered by a first power and receives an input signal that swings from a ground voltage level to a voltage level of the first power;    a level-down shifter which converts the output of the first power circuit from a voltage level of the first power to an output having a voltage level of a second power; and    a second power circuit having an input and an output, powered by the second power and receives the output of the level-down shifter, and outputs an output signal that swings from ground to the voltage level of the second power, wherein the level-down shifter comprises:    a first inverter, which is driven by a second power and receives the output of the first power circuit;    a second inverter, which is driven by the first power and receives the output of the first power circuit;    a PMOS transistor whose source is connected to the second power and whose gate is connected to an output of the first inverter; and    an NMOS transistor whose source is connected to ground, whose gate is connected to an output of the second inverter, and whose drain is connected to a drain of the PMOS transistor.