High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation

Abstract

A semiconductor device having a lateral channel with contacts on opposing surfaces thereof. The semiconductor device includes a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes an isolation layer above the conductive substrate, a lateral channel above the isolation layer and a drain contact above the lateral channel. The semiconductor device further includes a gate located in a gate recess interposed between the lateral channel and the drain contact and a drain formed by at least one source/drain contact layer interposed between the lateral channel and the drain contact. The drain is offset on one side of the gate by a gate-to-drain separation distance. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the source contact and the lateral channel.

1 . A semiconductor device, comprising: 
 a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof;    an isolation layer oppositely doped from and above said conductive substrate;    a lateral channel above said isolation layer;    a drain contact above said lateral channel;    a gate located in a gate recess interposed between said lateral channel and said drain contact;    a drain formed by at least one source/drain contact layer interposed between said lateral channel and said drain contact, and offset from said gate by a gate-to-drain separation distance; and    an interconnect that connects said lateral channel to said conductive substrate operable to provide a coupling between said source contact and said lateral channel.    
   
   
       2 . The semiconductor device as recited in  claim 1  wherein said gate-to-drain separation distance is equal to or greater than 1.5 μm.  
   
   
       3 . The semiconductor device as recited in  claim 1  further comprising a buffer layer interposed between said conductive substrate and said isolation layer.  
   
   
       4 . The semiconductor device as recited in  claim 1 , further comprising: 
 a spacer layer above said isolation layer;    a buffer layer above said spacer layer;    a modulation doped barrier layer above said spacer layer; and    another spacer layer above said barrier layer.    
   
   
       5 . The semiconductor device as recited in  claim 4  wherein said buffer layer is an alternating aluminum-gallium arsenide/gallium arsenide (“AlGaAs/GaAs”) super-lattice buffer.  
   
   
       6 . The semiconductor device as recited in  claim 1 , further comprising: 
 a spacer layer above said lateral channel;    a barrier layer above said spacer layer;    a recess layer above said barrier layer; and    an etch stop layer above said recess layer.    
   
   
       7 . The semiconductor device as recited in  claim 6  wherein said spacer layer is modulation doped to a level of about 1.2×10 12  cm −2  or less.  
   
   
       8 . The semiconductor device as recited in  claim 1  further comprising a metal layer and a drain post interposed between said at least one source/drain contact layer and said drain contact.  
   
   
       9 . The semiconductor device as recited in  claim 1  further comprising a dielectric layer interposed between said at least one source/drain contact layer and said drain contact.  
   
   
       10 . The semiconductor device as recited in  claim 1  wherein said lateral channel is pseudomorphic.  
   
   
       11 . A method of forming a semiconductor device, comprising: 
 providing a conductive substrate;    forming a source contact on a bottom surface of said conductive substrate;    forming an isolation layer oppositely doped from and above said conductive substrate;    forming a lateral channel above said isolation layer;    forming a drain contact above said lateral channel;    forming a gate in a gate recess interposed between said lateral channel and said drain contact;    forming a drain with at least one source/drain contact layer interposed between said lateral channel and said drain contact, and offset from said gate by a gate-to-drain separation distance; and    forming an interconnect that connects said lateral channel to said conductive substrate operable to provide a coupling between said source contact and said lateral channel.    
   
   
       12 . The method as recited in  claim 11  wherein said gate-to-drain separation distance is equal to or greater than 1.5 μm.  
   
   
       13 . The method as recited in  claim 11  further comprising forming a buffer layer interposed between said conductive substrate and said isolation layer.  
   
   
       14 . The method as recited in  claim 11 , further comprising: 
 forming a spacer layer above said isolation layer;    forming a buffer layer above said spacer layer;    forming a modulation doped barrier layer above said spacer layer; and    forming another spacer layer above said barrier layer.    
   
   
       15 . The method as recited in  claim 14  wherein said buffer layer is an alternating aluminum-gallium arsenide/gallium arsenide (“AlGaAs/GaAs”) super-lattice buffer.  
   
   
       16 . The method as recited in  claim 11 , further comprising: 
 forming a spacer layer above said lateral channel;    forming a barrier layer above said spacer layer;    forming a recess layer above said barrier layer; and    forming an etch stop layer above said recess layer.    
   
   
       17 . The method as recited in  claim 16  wherein said spacer layer is modulation doped to a level of about 1.2×10 12  cm 2  or less.  
   
   
       18 . The method as recited in  claim 11  further comprising forming a metal layer and a drain post interposed between said at least one source/drain contact layer and said drain contact.  
   
   
       19 . The method as recited in  claim 11  further comprising forming a dielectric layer interposed between said at least one source/drain contact layer and said drain contact.  
   
   
       20 . The method as recited in  claim 11  wherein said lateral channel is pseudomorphic.