Interconnection in an insulating layer on a wafer

Abstract

An interconnection in an insulating layer on a wafer is described herein. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.

1 . An interconnection in an insulating layer on a wafer, comprising: 
 a wafer having a plurality of conductive lines thereon;    an insulating layer disposed over the wafer to cover the conductive lines, wherein the insulating layer has two via holes that expose two of the conductive lines;    two pattern marks disposed inside the via holes and electrically connected to the two conductive lines, wherein the top surface of the two pattern marks are higher than the top surface of the insulating layer; and    a conductive layer covering at least the pattern marks and the insulating layer between the pattern marks so that the two conductive lines are electrically connected.    
   
   
       2 . The interconnection of  claim 1 , wherein the material constituting the pattern marks is selected from a group consisting of tungsten, platinum, gold, copper, aluminum and a combination thereof.  
   
   
       3 . The interconnection of  claim 1 , wherein the material constituting the conductive layer is selected from a group consisting of tungsten, platinum, gold, copper, aluminum and a combination thereof.  
   
   
       4 . The interconnection of  claim 1 , wherein the insulating layer is a passivation layer.  
   
   
       5 . The interconnection of  claim 1 , wherein the material constituting the insulating layer comprises silicon nitride or silicon oxide.