256 Meg dynamic random access memory

Abstract

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

1 . A voltage reference circuit for supplying a reference voltage in response to an external voltage, comprising: 
 a current source for receiving the external voltage and for supplying a current to a node;    a diode stack having an adjustable impedance for draining current from said node;    a current mirror connected in parallel with said current source and said diode stack;    a first transistor having a base terminal responsive to a voltage produced at said node, an emitter terminal connected to ground, and a collector terminal connected to said external voltage, said first transistor for producing the reference voltage available at said collector terminal of said first transistor; and    a second transistor having a base terminal responsive to said reference voltage, a collector terminal connected to said external voltage, and an emitter terminal connected to ground.    
   
   
       2 . The voltage reference circuit of  claim 1  wherein said diode stack comprises a plurality of transistors connected in series, with each transistor's gate connected to a common potential, and a plurality of switches each for selectively shunting one of said transistors.  
   
   
       3 . The voltage reference circuit of  claim 2  wherein said plurality of switches are controlled by a plurality of fuses, and wherein opening certain of said fuses turns its associated switch on, and wherein opening certain other of said fuses turns its associated switch off.  
   
   
       4 . The voltage reference circuit of  claim 2  wherein said plurality of transistors includes a first plurality of field effect transistors and wherein said plurality of switches includes a second plurality of field effect transistors.  
   
   
       5 . The voltage reference circuit of  claim 1  additionally comprising a pull-up stage for receiving said reference voltage, said pull-up stage connected between the external voltage and ground.  
   
   
       6 . The voltage reference circuit of  claim 5 , said pull-up stage comprising a plurality of diodes connected between the external voltage and ground.  
   
   
       7 . A voltage reference circuit in combination with an amplifier, comprising: 
 a bus for carrying an external voltage;    a current source;    a diode stack having an adjustable impedance, said diode stock connected in series with said current source between said bus carrying said external reference voltage and ground;    a current mirror connected in parallel with said series connect current source and diode stack;    a first transistor having a base terminal responsive to a voltage at a junction between said series connected current source and diode stack, and a collector terminal connected to said external voltage source, the reference voltage being available at said collector terminal of said first transistor;    a second transistor having a base terminal responsive to said reference voltage and a collector terminal connected to said external voltage; and    an amplifier responsive to said reference voltage for supplying an output voltage to an output voltage bus.    
   
   
       8 . The combination of  claim 7  additionally comprising a switch for connecting said bus carrying said external voltage to said output voltage bus when said external voltage is below a first predetermined value.  
   
   
       9 . The combination of  claim 7  additionally comprising a pull-up stage connected between said bus carrying said external voltage and ground, and wherein the external voltage is provided to said amplifier by said pull-up stage when the external voltage exceeds a predetermined value.  
   
   
       10 . The combination of  claim 9 , said pull-up stage comprising a plurality of diodes connected between said bus carrying said external voltage and ground.  
   
   
       11 . A method of supplying an output voltage in response to an external voltage having a powerup range and an operating range, said method comprising: 
 supplying the external voltage as the output voltage when the external voltage is in the powerup range;    producing a reference signal in response to said external voltage;    producing a copy of said reference signal; and    amplifying said copy by a factor greater than unity to provide the output voltage when the external voltage is in the operating range.    
   
   
       12 . The method of  claim 11  wherein said producing a reference signal includes generating a current related to the external voltage, applying the current to a circuit node, and draining the current from the circuit node through an adjustable impedance.  
   
   
       13 . The method of  claim 12  additionally comprising adjusting the impedance to modify the value of the reference signal.  
   
   
       14 . The method of  claim 13  wherein said adjusting the impedance includes one of opening or closing a fuse.  
   
   
       15 . The method of  claim 11  wherein said external signal has a burn-in range, said method additionally comprising pulling up the reference voltage so that the reference voltage substantially tracks the external voltage when the external voltage is in the burn-in range.  
   
   
       16 . The method of  claim 11  additionally comprising maintaining a dependence between the output voltage and the external voltage when said external voltage is in the operating range.  
   
   
       17 . A method of supplying an output voltage in response to an external voltage having a powerup range, an operating range, and a burn-in range, said method comprising: 
 connecting a bus carrying the output voltage to the external voltage when the external voltage is in the powerup range;    producing a reference signal, producing a copy of the reference signal, amplifying the copy of the reference signal, and supplying the amplified copy of the reference signal to the bus carrying the output voltage when the external voltage is in said operating mode;    amplifying the external voltage and supplying the amplified external voltage to the bus carrying the output voltage when the external voltage is in said burn-in range.    
   
   
       18 . The method of  claim 17  additionally comprising maintaining a dependence between the output voltage and the external voltage when said external voltage is in the operating range.