Cryptographic system component

Abstract

In general, in aspect, the disclosure describes a system integrated on a single die that includes a first processor core to receive commands from at least one other processor core to perform at least one specified transformative operation on specified data, multiple processing units to perform transformative operations on data, a shared memory, and logic to transfer data between a one of the set of multiple processing units and the shared memory.

1 . A system integrated on a single die, comprising: 
 a first processor core to receive commands from at least one other processor core, the commands requesting performance of at least one specified transformative operation on specified data;    a set of multiple processing units comprising logic to perform transformative operations on data;    a shared memory coupled to the set of multiple processing units; and    logic to receive commands from the first processor core, the commands to transfer data between a one of the set of multiple processing units and the shared memory.    
   
   
       2 . The system of  claim 1 , wherein at least two processing units of the multiple processing units perform the same operations and wherein at least two processing units of the multiple processing units perform different operations.  
   
   
       3 . The system of  claim 1 , wherein at least one of the processing units of the set of multiple processing units comprises a processing unit to perform encryption.  
   
   
       4 . The system of  claim 1 , wherein at least one of the processing units of the set of multiple processing units comprises at least one programmable processing unit.  
   
   
       5 . The system of  claim 4 , wherein the at least one programmable processing unit receives instructions to execute from the shared memory.  
   
   
       6 . The system of  claim 1 , wherein each processing unit in the set of multiple processing units comprises a processing unit having an input buffer to store data transferred from the shared memory, an output buffer to store data to be transferred to the shared memory, and a logic block to operate on data received by the input buffer.  
   
   
       7 . The system of  claim 1 , wherein the transformative operation comprises at least one of: data encryption, data decryption, and data hashing.  
   
   
       8 . The system of  claim 1 , wherein the commands comprise commands specifying a particular processing unit of the set of multiple processing units and an operation selected from one of the following group: transfer of data from the shared memory to the particular processing unit and transfer of data from the particular processing unit to the shared memory.  
   
   
       9 . The system of  claim 1 , further comprising logic to transfer data from the shared memory to a randomly accessible memory external to the silicon die and to transfer data from the randomly accessible memory external to the silicon die to the shared memory.  
   
   
       10 . The system of  claim 1 , wherein the first processor core comprises a processor core having storage for multiple program counters to provide multiple threads of execution.  
   
   
       11 . The system of  claim 1 , wherein the logic enqueues the received commands based on a target one of the processing units specified by the command.  
   
   
       12 . The system of  claim 11 , wherein the logic enqueues the received commands based on whether a command specifies a transfer to the target one of the processing units or a command specifies a transfer from the target one of the processing units.  
   
   
       13 . The system of  claim 1 , further comprising a first bus coupling the first processor core with the at least one other processor core, and a second bus coupling the logic and the processing units.  
   
   
       14 . The system of  claim 1 , wherein the at least one other processor core comprises multiple processor cores.  
   
   
       15 . A method comprising: 
 receiving a command at a first processor core, the first processor core providing multiple threads of program execution, the command specifying at least one cryptographic operation to perform on specified data;    causing a thread of the multiple threads to: 
 cause the data to be transferred to a shared memory;  
 cause multiple ones of a set of multiple processing units coupled to the shared memory to perform operations based on the data in a sequence specified by the thread, each of the multiple ones of the set of multiple processing units operating on data from the shared memory and returning processed data to the shared memory.  
   
   
   
       16 . The method of  claim 15 , wherein the at least one cryptographic operation comprises at least one selected from a group comprising: encryption, decryption, authentication, and generation of a cryptographic key.  
   
   
       17 . The method of  claim 15 , wherein causing multiple ones of the set of multiple processing units to perform operations based on the data comprises transferring executable instructions of a program to implement at least one of the operations to at least one of the multiple processing units in response to the command, the executable instructions including at least one conditional branch of execution.  
   
   
       18 . A computer program disposed on a computer readable medium, the program comprising instructions for causing a processor to: 
 receive a command specifying at least one cryptographic operation to perform on specified data;    cause a thread of the multiple threads to service the command, the thread comprising a thread to: 
 cause the data to be transferred to a shared memory;  
 cause multiple ones of a set of multiple processing units coupled to the shared memory to perform operations based on the data in a sequence specified by the thread, each of the multiple ones of the set of multiple processing units operating on data from the shared memory and returning processed data to the shared memory.  
   
   
   
       19 . The program of  claim 18 , wherein the at least one cryptographic operation comprises at least one selected from a group comprising: encryption, decryption, authentication, and generation of a cryptographic key.  
   
   
       20 . The program of  claim 18 , wherein causing multiple ones of the set of multiple processing units to perform operations based on the data comprises transferring executable instructions of a program to implement at least one of the operations to at least one of the multiple processing units in response to the command, the executable instructions including at least one conditional branch of execution.  
   
   
       21 . A system, comprising: 
 an Ethernet MAC (media access controller); and    multiple processor cores integrated on a single die, a first of the processor cores to receive commands from the other processor cores to perform at least one specified transformative operation on specified data;    a set of multiple processing units comprising logic to perform transformative operations on data;    a shared memory coupled to the set of multiple processing units; and    logic to receive commands from the first processor core, the commands to transfer data between a one of the set of multiple processing units and the shared memory.    
   
   
       22 . The system of  claim 21 , wherein at least one of the processing units of the set of multiple processing units comprises a processing unit having dedicated hardware to perform encryption.  
   
   
       23 . The system of  claim 21 , 
 wherein at least one of the processing units of the set of multiple processing units comprises at least one programmable processing unit; and    wherein the at least one programmable processing unit receives instructions to execute from the shared memory in response to a command received by the logic to transfer data from the shared memory to the programmable processing unit.    
   
   
       24 . The system of  claim 21 , wherein each processing unit in the set of multiple processing units comprises a processing unit having an input buffer to store data transferred from the shared memory, an output buffer to store data to be transferred to the shared memory, and a logic block to operate on data received by the input buffer.  
   
   
       25 . The system of  claim 21 , wherein the transformative operation comprises at least one of: data encryption, data decryption, and data hashing.  
   
   
       26 . The system of  claim 21 , wherein the commands comprise commands specifying a particular processing unit of the set of multiple processing units and an operation selected from one of the following group: transfer data from the shared memory to the particular processing unit and transfer data from the particular processing unit to the shared memory.  
   
   
       27 . The system of  claim 21 , further comprising a first bus coupling the first processor core with the at least one other processor core, and a second bus coupling the logic and the processing units.