Inventor · disambiguated record
William C. Hasenplaugh
Also filed as: HASENPLAUGH WILLIAM · HASENPLAUGH WILLIAM C
34 granted patents·7 pending applications·278 citations·filing 2005–2019
97Inventor score
Top patents by PatentIndex Score
41 records- 0196US9104474B2Variable precision floating point multiply-add circuitINTEL CORP·Filed 2012·Granted Aug 11, 2015·75 cites·27 claims
- 0292US7725657B2Dynamic quality of service (QoS) for a shared cacheINTEL CORP·Filed 2007·Granted May 25, 2010·33 cites·17 claims
- 0389US9294419B2Scalable multi-layer 2D-mesh routersINTEL CORP·Filed 2013·Granted Mar 22, 2016·12 cites·30 claims
- 0489US8020142B2Hardware acceleratorINTEL CORP·Filed 2006·Granted Sep 13, 2011·21 cites·23 claims
- 0589US7725624B2System and method for cryptography processing units and multiplierINTEL CORP·Filed 2005·Granted May 25, 2010·20 cites·20 claims
- 0688US8407421B2Cache spill management techniques using cache spill predictionSTEELY JR SIMON C·Filed 2009·Granted Mar 26, 2013·17 cites·29 claims
- 0788US7930337B2Multiplying two numbersINTEL CORP·Filed 2006·Granted Apr 19, 2011·21 cites·23 claims
- 0885US8073892B2Cryptographic system, method and multiplierFEGHALI WAJDI K·Filed 2005·Granted Dec 6, 2011·22 cites·32 claims
- 0981US10402168B2Low energy consumption mantissa multiplication for floating point multiply-add operationsINTEL CORP·Filed 2016·Granted Sep 3, 2019·3 cites·24 claims
- 1081US9317263B2Hardware compilation and/or translation with fault detection and roll back functionalityINTEL CORP·Filed 2014·Granted Apr 19, 2016·6 cites·28 claims
- 1180US9262327B2Signature based hit-predicting cacheSTEELY JR SIMON C·Filed 2012·Granted Feb 16, 2016·6 cites·26 claims
- 1280US9037804B2Efficient support of sparse data structure accessSTEELY JR SIMON C·Filed 2011·Granted May 19, 2015·5 cites·13 claims
- 1379US10379855B2Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registersINTEL CORP·Filed 2016·Granted Aug 13, 2019·2 cites·23 claims
- 1476US9251073B2Update mask for handling interaction between fills and updatesINTEL CORP·Filed 2012·Granted Feb 2, 2016·4 cites·21 claims
- 1575US11068264B2Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registersINTEL CORP·Filed 2019·Granted Jul 20, 2021·1 cites·19 claims
- 1673US7900022B2Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instructionINTEL CORP·Filed 2006·Granted Mar 1, 2011·6 cites·20 claims
- 1771US8769201B2Technique for controlling computing resourcesHASENPLAUGH WILLIAM·Filed 2008·Granted Jul 1, 2014·7 cites·28 claims
- 1870US9740617B2Hardware apparatuses and methods to control cache line coherenceINTEL CORP·Filed 2014·Granted Aug 22, 2017·2 cites·24 claims
- 1970US9727482B2Address range priority mechanismINTEL CORP·Filed 2016·Granted Aug 8, 2017·1 cites·16 claims
- 2066US9201792B2Short circuit of probes in a chainSTEELY JR SIMON C·Filed 2011·Granted Dec 1, 2015·2 cites·12 claims
- 2164US9250682B2Distributed power management for multi-core processorsINTEL CORP·Filed 2012·Granted Feb 2, 2016·1 cites·22 claims
- 2263US9418016B2Method and apparatus for optimizing the usage of cache memoriesSTEELY JR SIMON C·Filed 2010·Granted Aug 16, 2016·1 cites·26 claims
- 2363US9146871B2Retrieval of previously accessed data in a multi-core processorSTEELY JR SIMON C·Filed 2011·Granted Sep 29, 2015·1 cites·20 claims
- 2463US8229109B2Modular reduction using foldingHASENPLAUGH WILLIAM C·Filed 2006·Granted Jul 24, 2012·4 cites·22 claims
- 2560US7475229B2Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exitINTEL CORP·Filed 2006·Granted Jan 6, 2009·1 cites·17 claims
- 2656US7827471B2Determining message residue using a set of polynomialsINTEL CORP·Filed 2006·Granted Nov 2, 2010·3 cites·17 claims
- 2755US8893094B2Hardware compilation and/or translation with fault detection and roll back functionalityCHEE NICHOLAS CHENG HWA·Filed 2011·Granted Nov 18, 2014·1 cites·30 claims
- 2853US9934146B2Hardware apparatuses and methods to control cache line coherencyINTEL CORP·Filed 2014·Granted Apr 3, 2018·0 cites·25 claims
- 2952US9734069B2Multicast tree-based data distribution in distributed shared cacheINTEL CORP·Filed 2014·Granted Aug 15, 2017·0 cites·20 claims
- 3048US9588889B2Domain stateSTEELY JR SIMON C·Filed 2011·Granted Mar 7, 2017·0 cites·35 claims
- 3148US8438335B2Probe speculative address fileSTEELY JR SIMON C·Filed 2010·Granted May 7, 2013·0 cites·18 claims
- 3248US2007192626A1Exponent windowingFEGHALI WAJDI K·Filed 2006·Application pending·0 cites
- 3347US7801299B2Techniques for merging tablesINTEL CORP·Filed 2006·Granted Sep 21, 2010·0 cites·19 claims
- 3446US2007157030A1Cryptographic system componentFEGHALI WAJDI K·Filed 2005·Application pending·0 cites
- 3543US9477610B2Address range priority mechanismSTEELY JR SIMON·Filed 2011·Granted Oct 25, 2016·0 cites·19 claims
- 3642US2014006716A1Data control using last accessor informationSTEELEY JR SIMON C·Filed 2011·Application pending·0 cites
- 3742US2011106872A1Method and apparatus for providing an area-efficient large unsigned integer multiplierHASENPLAUGH WILLIAM·Filed 2008·Application pending·0 cites
- 3841US10102124B2High bandwidth full-block write commandsSTEELY JR SIMON C·Filed 2011·Granted Oct 16, 2018·0 cites·18 claims
- 3940US2007192571A1Programmable processing unit providing concurrent datapath operation of multiple instructionsFEGHALI WAJDI K·Filed 2006·Application pending·0 cites
- 4036US2012246407A1Method and system to improve unaligned cache memory accessesHASENPLAUGH WILLIAM C·Filed 2011·Application pending·0 cites
- 4123US2011248755A1Cross-feedback phase-locked loop for distributed clocking systemsHASENPLAUGH WILLIAM C·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →