Flexible scan architecture

Abstract

A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

1 . A processor comprising: 
 a first clock circuit to clock a first functional unit while the first functional unit is not being tested; a second clock circuit to clock a second functional unit independently of the first clock circuit while the second functional unit is being tested.    
   
   
       2 . The processor of claim  32  wherein the second clock circuit comprises a cluster test controller, a unit test controller, and a local test clock controller.  
   
   
       3 . The processor of claim  33  wherein the functional unit comprises a plurality of functional units.  
   
   
       4 . The processor of claim  34  further comprising a third clock circuit to at least partially control the plurality of functional units independently of the functional clock circuit.  
   
   
       5 . The processor of claim  35  wherein the third clock circuit comprises a master clock generation unit and a slave clock generation unit.  
   
   
       6 . The processor of claim  36  wherein the first clock circuit is to couple a functional clock signal to the first and second functional units during normal operation of the first and second functional units.  
   
   
       7 . The processor of claim  37  wherein the second clock circuit is to couple a functional clock signal to the first and second functional units during testing of the first and second functional units.