Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed

Abstract

A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.

1 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   a first insulation film formed on the semiconductor substrate;   a first gate electrode formed on the first insulation film;   a second insulation film formed on an upper surface and a side surface of the first gate electrode; and   a second gate electrode formed on the second insulation film,   wherein an entirety of a part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer, and at least a portion of a part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.   
   
   
       2 . The device according to  claim 1 , wherein a part of the second insulation film, which is in contact with the second gate electrode, is a silicon nitride film. 
   
   
       3 . The device according to  claim 1 , further comprising a selection transistor formed on the semiconductor substrate, the selection transistor including the first insulation film, the first gate electrode, a second insulation film, and the second gate electrode. 
   
   
       4 . The device according to  claim 3 , wherein the second insulation film of the selection transistor has an opening, and a conductor, which connects the first gate electrode and the second gate electrode, is formed in the opening. 
   
   
       5 . The device according to  claim 4 , wherein the conductor is a silicon layer. 
   
   
       6 . The device according to  claim 4 , wherein the conductor is formed of an insulation layer and a silicide layer formed on the insulation layer. 
   
   
       7 . The device according to  claim 1 , wherein the nonvolatile semiconductor memory device is a NAND-type nonvolatile semiconductor memory device. 
   
   
       8 . The device according to  claim 1 , wherein the nonvolatile semiconductor memory device is a NOR-type nonvolatile semiconductor memory device. 
   
   
       9 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   a memory cell including a first insulation film formed on the semiconductor substrate, a first gate electrode formed on the first insulation film, a second insulation film formed on an upper surface and a side surface of the first gate electrode, and a second gate electrode formed on the second insulation film; and   a selection transistor including a third gate electrode formed on the semiconductor substrate via the first insulation film,   wherein an entirety of a part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer, and a part of the third gate electrode, which is in contact with the first insulation film, is a silicon layer.   
   
   
       10 . The device according to  claim 9 , wherein a part of the second insulation film, which is in contact with the second gate electrode, is a silicon nitride film. 
   
   
       11 . The device according to  claim 9 , wherein the third gate electrode has a stacked gate structure comprising the first gate electrode, the second insulation film, the second gate electrode and a conductor which is filled in an opening formed in the second insulation film. 
   
   
       12 . The device according to  claim 11 , wherein the third gate electrode is configured such that a part of the first gate electrode, which is in contact with the second insulation film, and the conductor are silicide layers. 
   
   
       13 . The device according to  claim 9 , wherein the nonvolatile semiconductor memory device is a NAND-type nonvolatile semiconductor memory device. 
   
   
       14 . The device according to  claim 9 , wherein the nonvolatile semiconductor memory device is a NOR-type nonvolatile semiconductor memory device. 
   
   
       15 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   a memory cell including a first insulation film formed on the semiconductor substrate, a first gate electrode formed on the first insulation film, a second insulation film formed on an upper surface and a side surface of the first gate electrode, and a second gate electrode formed on the second insulation film; and   a selection transistor including a third gate electrode formed on the semiconductor substrate via the first insulation film,   wherein an entirety of a part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer, and at least a portion of a part of the second gate electrode, which is located on the side surface of the first gate electrode, and a part of the third gate electrode, which is in contact with the first insulation film, are silicon layers.   
   
   
       16 . The device according to  claim 15 , wherein the third gate electrode has a stacked gate structure comprising the first gate electrode, the second insulation film, the second gate electrode and a conductor which is filled in an opening formed in the second insulation film. 
   
   
       17 . The device according to  claim 15 , wherein the third gate electrode is configured such that a part of the first gate electrode, which is in contact with the second insulation film, and the conductor are silicide layers. 
   
   
       18 . The device according to  claim 15 , wherein the nonvolatile semiconductor memory device is a NAND-type nonvolatile semiconductor memory device. 
   
   
       19 . The device according to  claim 15 , wherein the nonvolatile semiconductor memory device is a NOR-type nonvolatile semiconductor memory device. 
   
   
       20 . The device according to  claim 9 , wherein the third gate electrode of the select transistor includes an insulating film for stopping siliciding.