Semiconductor wafer with high thermal conductivity

Abstract

This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

1 . A semiconductor wafer comprising: 
 a substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge, wherein the substrate has a dopant concentration below about 1×10 17  carriers/cm 3 ;    a silicon device layer; and    a silicon protective layer disposed between the device layer and the substrate, the protective layer being doped with a dopant concentration between about 6.0×10 17  carriers/cm 3  and about 1.0×10 20  carriers/cm 3  and having a thickness of at least about 0.5 μm.    
     
     
         2 . The semiconductor wafer of  claim 1  wherein the protective layer has a thickness between about 1 μm and about 5 μm.  
     
     
         3 . The semiconductor wafer of  claim 1  wherein the protective layer is doped with a dopant concentration between about 8.5×10 18  carriers/cm 3  and about 2.0×10 19  carriers/cm 3 .  
     
     
         4 . The semiconductor wafer of  claim 1  wherein the protective layer is doped with a dopant concentration between about 3.2×10 18  carriers/cm 3  and about 8.5×10 18  carriers/cm 3 .  
     
     
         5 . The semiconductor wafer of  claim 3  wherein the substrate has a dopant concentration between about 5×10 14  carriers/cm 3  and about 1×10 16  carriers/cm 3 .  
     
     
         6 . The semiconductor wafer of  claim 1  wherein the device layer is doped with a P-type dopant.  
     
     
         7 . The semiconductor wafer of  claim 1  wherein the device layer is doped with boron.  
     
     
         8 . The semiconductor wafer of  claim 1  wherein: 
 the substrate is doped with a P-type dopant in a concentration between about 5×10 14  carriers/cm 3  and about 1×10 16  carriers/cm 3 ;    the protective layer is doped with a P-type dopant in a concentration between about 3.2×10 18  carriers/cm 3  and about 2.0×10 19  carriers/cm 3 , and has a thickness between about 1 μm and about 10 μm; and    the device layer is doped with a P-type dopant in a concentration between about 1×10 14  carriers/cm 3  and about 4×10 16  carriers/cm 3 .    
     
     
         9 . The semiconductor wafer of  claim 1  wherein: 
 the protective layer is doped with a P-type dopant in a concentration above about 1.0×10 19  carriers/cm 3  and about 1.0×10 20  carriers/cm 3 , and has a thickness of less than about 5 μm; and    the device layer is between about 2 μm and about 15 μm thick.    
     
     
         10 . The semiconductor wafer of  claim 9  wherein the protective layer has a thickness of less than about 2 μm and the device layer is between about 2 μm and about 5 μm thick.  
     
     
         11 . A process for the preparation of a semiconductor wafer comprising a substrate having a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge, wherein the substrate has a dopant concentration below about 1×10 17  carriers/cm 3 , the process comprising: 
 forming a protective layer on the front surface of the substrate, the protective layer being doped with a dopant concentration between about 6.0×10 17  carriers/cm 3  and about 1.0×10 20  carriers/cm 3  and having a thickness of at least about 0.5 μm; and    forming a device layer on the exposed surface of the protective layer parallel to the front surface of the substrate, the device layer being doped with a dopant concentration below about 1×10 17  carriers/cm 3 .    
     
     
         12 . The process of  claim 11  wherein the protective layer is formed by exposing the surface of the substrate to an atmosphere comprising silicon and a dopant to deposit a silicon epitaxial layer.  
     
     
         13 . The process of  claim 11  wherein the protective layer is formed by implanting dopant ions in the surface of the substrate.  
     
     
         14 . The process of  claim 11  wherein the first layer is formed by exposing the surface of the substrate to a gas comprising a dopant to form a gas phase-doped layer.  
     
     
         15 . The process of  claim 11  wherein the protective layer has a thickness between about 1 μm and about 5 μm.  
     
     
         16 . The process of  claim 11  wherein the protective layer is doped with a dopant concentration between about 8.5×10 18  carriers/cm 3  and about 2.0×10 19  carriers/cm 3 .  
     
     
         17 . The process of  claim 11  wherein the protective layer is doped with a dopant concentration between about 3.2×10 18  carriers/cm 3  and about 8.5×10 18  carriers/cm 3 .  
     
     
         18 . The process of  claim 16  wherein the substrate has a dopant concentration between about 5×10 14  carriers/cm 3  and about 1×10 16  carriers/cm 3 .  
     
     
         19 . The process of  claim 11  wherein the device layer is doped with a P-type dopant.  
     
     
         20 . The process of  claim 11  wherein the device layer is doped with boron.  
     
     
         21 . The process of  claim 11  wherein: 
 the substrate is doped with a P-type dopant in a concentration between about 5×10 14  carriers/cm 3  and about 1×10 16  carriers/cm 3 ;    the protective layer is doped with a P-type dopant in a concentration between about 3.2×10 18  carriers/cm 3  and about 2.0×10 19  carriers/cm 3 , and has a thickness between about 1 μm and about 10 μm; and    the device layer is doped with a P-type dopant in a concentration between about 1×10 14  carriers/cm 3  and about 4×10 16  carriers/cm 3 .    
     
     
         22 . The process of  claim 11  wherein: 
 the substrate is doped with a P-type dopant in a concentration between about 5×10 14  carriers/cm 3  and about 1×10 16  carriers/cm 3 ;    the protective layer is doped with a P-type dopant in a concentration between about 1.0×10 19  carriers/cm 3  and about 1.0×10 20  carriers/cm 3 , and has a thickness of less than about 3 μm;    the device layer has a thickness between about 2 μm and about 15 μm; and    the process further comprises a first etching step, wherein the back surface of the substrate is exposed to an alkaline etchant for a time period sufficient to remove substantially all of the substrate, exposing the protective layer.    
     
     
         23 . The process of  claim 22  wherein the etchant comprises a compound selected from the group consisting of potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide, and combinations thereof.  
     
     
         24 . The process of  claim 22  wherein the process further comprises exposing the protective layer exposed by the first etch to a second etching step, wherein the protective layer is exposed to an acidic etchant.  
     
     
         25 . The process of  claim 24  wherein the acidic etchant comprises a solution of hydrofluoric, nitric, and acetic acids.  
     
     
         26 . The process of  claim 22  wherein the protective layer has a thickness of less than about 2 μm and the device layer is between about 2 μm and about 5 μm thick.